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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to specify timing constraints between 2 memory ports

I have a design with 2 memory read ports (M1 and M2) connected as follows M1 ---> combinational-gates----> M2 i.e. M1's data out feeds the address of M2. M1 and M2 are clocked by the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

hi:

I have a follow up question: Will the generated clock trick in SDC work

for clock enables as well? If I move the logic to enables such that the 2 state

devices have the same clock but 2 derived clock enables, How can I specify

this in SDC?