How to recreate a timing failure on two different machines.
We have a continuous integration job run each night to build our FPGA images, this runs on a server that we don't have access to for day to day working, it is dedicated to running CI jobs.
Recently the job to build the FPGA images has developed an intermittent timing failure, some days it fails, some days it passes. I have since added a constraint to the QSF (
set_global_assignment -name SEED <value>) to try to make this deterministic and recreatable.
However, when I run the compilation locally on my development machine, the build reliably meets timing.
Is there a way that I've missed to ensure consistency of builds from different machines?
Context:
Running Quartus Pro 21.2
Hi,
As long as you did not make any changes to your design and are using the same environment (machine), then you will be able to reproduce the same timing results regardless how much time has passed.
Regards,
Nurina