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JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

How to recreate a timing failure on two different machines.

We have a continuous integration job run each night to build our FPGA images, this runs on a server that we don't have access to for day to day working, it is dedicated to running CI jobs. Recently ...
Hdl
Timing
  • Nurina's avatar
    Nurina
    2 years ago

    Hi,


    As long as you did not make any changes to your design and are using the same environment (machine), then you will be able to reproduce the same timing results regardless how much time has passed.


    Regards,

    Nurina


JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thank you very much for your reply sstrell.

Is there any way to make the compilation process somewhat deterministic? We have a requirement to be able to reproduce artifacts from a given repository state.

Do factors such as time of day/date affect the seed? Does the contents of a .mif/.hex file for initalising RAM contents have an effect?

So, for example, if I ran a compilation today, and then if I ran another compilation from the same repository state on the same machine two week later, would you expect the results to be the same?

When I was reading https://www.intel.com/content/www/us/en/docs/programmable/683145/21-3/change-fitter-placement-seeds.html it made no mention of different machines, etc. so I hoped there may be a way to do this.