Forum Discussion
Honored ContributorHow to get quartus_map to generate a netlist file for bottom-up synthesis
I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow. With the Xilinx tools I was able to run the XST synthesis tool on a set of source files and have it output/generate a single netlist representing that code (e.g. my_module_A.edf).
However, when I run quartus_map I don't see any netlist file like this being generated. How do I tell the Quartus synthesis tool to output this file? My standard development approach is to synthesize submodules A, B, and C all separately, and then pull all of those netlists into a top-level wrapper module called MY_DESIGN_TOP. In other words, I want to instanciate modules A, B, and C in the MY_DESIGN_TOP. But modules A, B, and C would already be synthesized into their own individual netlists. Then I would source those EDIF netlist files (rather than the original HDL source) when running quartus_map on MY_DESIGN_TOP. I know how to do this with the Xilinx tools but need a little help with the Quartus software. I fear that in order to do this though I need to have "incremental compilation" which is disabled in the web-edition. Someone please say it aint so.... :( Thanks!11 Replies
Altera_ForumI can't help you with your specific compilation method. However, I also prefer to ditch the GUI and use scripts or makefiles to build hardware designs. Tcl scripts can be used for Altera Quartus, Xilinx ISE, and Lattice Diamond (and of course for simulation in Modelsim).
However, I'm quite happy to give the synthesis tool VHDL directly and let it optimize the design across modules. I routinely fill large FPGAs to above 95% resource utilization, and get operating frequencies in the hundreds of MHz (the designs usually become thermally limited). I'm curious as to why you want to generate netlists at the level of an individual module. Is this some historical design method that you've been sticking with? Or related to the use of multiple clock domains? Try compiling the HDL directly, and see what the synthesis tool reports. If you have an SDC file that constraints the timing correctly, you should be able to get things working well. Cheers, Dave- Altera_Forum
"I'm curious as to why you want to generate netlists at the level of an individual module."
There are two primary reasons that I prefer to synthesize the design as smaller modules: 1) It drastically decreases implementation time for large designs (since code that has not changed does not get needlessly recompiled). 2) When synthesizing smaller modules as individual netlists it is easier to see how small changes effect the behavior (since diff'ing a few hundred line synthesis report is easier than diff'ing a ten-thousand line synth report). # 1 is obviously the primary reason though. It stinks having to wait for a huge design to resynthesize just for a one-line change in a single state machine (for example). - Altera_Forum
take a look at the .tcl script in this project:
http://alterawiki.com/wiki/top_qxp_export you might need Subscription Edition to use .qxp files, I'm not sure - Altera_Forum--- Quote Start --- It drastically decreases implementation time for large designs (since code that has not changed does not get needlessly recompiled). --- Quote End --- Ok, thanks, this makes sense. Take a look a the Quartus Handbook. They have some incremental design tools, and I vaguely recall seeing a smart makefile helper function in there too. Supposedly it ensures that the tool will only recompile and P&R the design changes, rather than the whole design. I plan on reading through that stuff again sometime soon. If I find the specific information I am recalling, I'll add it to this discussion. Cheers, Dave
- Altera_Forum
Unfortunately, I think I've hit the worst case scenario. I keep hearing the solution of incremental compilation and using a QXP. Bad news is that I have confirmed that both of these features are only available with the Subscription Edition. :'(
So everyone's solutions are the correct answer....but unfortunately just inaccessible to a hobbyist such as myself. Oh well... - Altera_Forum
How about this alternative; design so that you only need to compile once, not incrementally. I use Modelsim and testbenches to get everything working nicely before I synthesize the design. Iteration at that point is related to adjusting timing constraints, rather than edit-and-recompile cycles.
Cheers, Dave - Altera_Forum
what family are you using? are your compilations really that long?
- Altera_Forum
"I use Modelsim and testbenches to get everything working nicely before I synthesize the design."
Okay, so I knew that suggestion was going to come up at some point. Hehe. I tend not to simulate that much anymore purely due to the fact that software-based simulation can just take wayyyyyyyyyyyyyyy too long to complete (or even get any useful data on large designs). Especially when you have to simulate with 'ps' timescale with a *serial* protocol. You could literally wait weeks to see any relevant data. This is why most of my debugging and verification is done using embedded ILAs. "what family are you using? are your compilations really that long?" It depends on the project. I've got some at-home hobby projects that target cyclone II which take 45min-1hr at most. But I have some larger projects at my employer that target Stratix devices which take many hours to implement. Whatever the case, I would like to know how to do the bottom-up synthesis approach. But as we've already discovered, the solution has been found - you just need the subscription edition to do it. Oh well, I won't complain, the web edition is an extremely powerful tool as is and, hey, it's FREE!!! Pz! Jonathon - Altera_Forum--- Quote Start --- With the Xilinx tools I was able to run the XST synthesis tool on a set of source files and have it output/generate a single netlist representing that code (e.g. my_module_A.edf). --- Quote End --- Well, I think Altera has an similar process for generating post-synthesis EDIF netlists (the way Xilinx does it), it's just probably an extra step that you have to do manually. I remember being able to generate EDIF or VHDL/Verilog structural post-synthesis netlists using something called NativeLink. It's usually used for interoperability between Quartus and 3rd-party tools, such as generating a simulation netlist for ModelSim for example. But I guess you can use it for your own purpose (sub-compilations) as well. Regards, Daniel
- Altera_Forum
Hi,
You can try this, maybe it just works for you: Under Settings > EDA Tool Settings > Design Entry/Synthesis (or Simulation/whatever if you want) > Specify any Tool Name (can be Custom too), there you can choose which format you want to export your post-synthesis netlist (you'll see the options "EDIF", "VHDL", "Verilog HDL" among the values of the drop-down list. Remember to run the "EDA Netlist Writer" after you're done changing these settings. Regards, Daniel
