How to get quartus_map to generate a netlist file for bottom-up synthesis

I can't help you with your specific compilation method. However, I also prefer to ditch the GUI and use scripts or makefiles to build hardware designs. Tcl scripts can be used for Altera Quartus, Xilinx ISE, and Lattice Diamond (and of course for simulation in Modelsim).

However, I'm quite happy to give the synthesis tool VHDL directly and let it optimize the design across modules. I routinely fill large FPGAs to above 95% resource utilization, and get operating frequencies in the hundreds of MHz (the designs usually become thermally limited).

I'm curious as to why you want to generate netlists at the level of an individual module. Is this some historical design method that you've been sticking with? Or related to the use of multiple clock domains? Try compiling the HDL directly, and see what the synthesis tool reports. If you have an SDC file that constraints the timing correctly, you should be able to get things working well.

Cheers,

Dave