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Honored Contributor
Honored ContributorHow to get quartus_map to generate a netlist file for bottom-up synthesis
I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow....
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- With the Xilinx tools I was able to run the XST synthesis tool on a set of source files and have it output/generate a single netlist representing that code (e.g. my_module_A.edf). --- Quote End --- Well, I think Altera has an similar process for generating post-synthesis EDIF netlists (the way Xilinx does it), it's just probably an extra step that you have to do manually. I remember being able to generate EDIF or VHDL/Verilog structural post-synthesis netlists using something called NativeLink. It's usually used for interoperability between Quartus and 3rd-party tools, such as generating a simulation netlist for ModelSim for example. But I guess you can use it for your own purpose (sub-compilations) as well. Regards, Daniel
