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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to get quartus_map to generate a netlist file for bottom-up synthesis

I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How about this alternative; design so that you only need to compile once, not incrementally. I use Modelsim and testbenches to get everything working nicely before I synthesize the design. Iteration at that point is related to adjusting timing constraints, rather than edit-and-recompile cycles.

Cheers,

Dave