Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to get quartus_map to generate a netlist file for bottom-up synthesis
I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow....
Altera_ForumHonored Contributor
Honored ContributorHi,
You can try this, maybe it just works for you: Under Settings > EDA Tool Settings > Design Entry/Synthesis (or Simulation/whatever if you want) > Specify any Tool Name (can be Custom too), there you can choose which format you want to export your post-synthesis netlist (you'll see the options "EDIF", "VHDL", "Verilog HDL" among the values of the drop-down list. Remember to run the "EDA Netlist Writer" after you're done changing these settings. Regards, Daniel
