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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to get quartus_map to generate a netlist file for bottom-up synthesis

I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

You can try this, maybe it just works for you:

Under Settings > EDA Tool Settings > Design Entry/Synthesis (or Simulation/whatever if you want) >

Specify any Tool Name (can be Custom too), there you can choose which format you want to export your post-synthesis netlist (you'll see the options "EDIF", "VHDL", "Verilog HDL" among the values of the drop-down list.

Remember to run the "EDA Netlist Writer" after you're done changing these settings.

Regards,

Daniel