How to get quartus_map to generate a netlist file for bottom-up synthesis

"I'm curious as to why you want to generate netlists at the level of an individual module."

There are two primary reasons that I prefer to synthesize the design as smaller modules:

1) It drastically decreases implementation time for large designs (since code that has not changed does not get needlessly recompiled).

2) When synthesizing smaller modules as individual netlists it is easier to see how small changes effect the behavior (since diff'ing a few hundred line synthesis report is easier than diff'ing a ten-thousand line synth report).

# 1 is obviously the primary reason though. It stinks having to wait for a huge design to resynthesize just for a one-line change in a single state machine (for example).