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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to create a neg-edge Write pulse, from a pos-edge Write pulse?

I have a active-high signal that transitions on the positive edge of its clock when it has data ready to be written to memory.

I also have ram memory (uses same clock) but expects the write request signal to transition on the negative edge of the clock (and stay high until the following negative edge of the clock).

If I try driving the memory's wr_req directly from the data source then both the clock and wr_req transition at the same time and the memory doesn't get the data.

How can I delay the data source's write pulse such that it goes high (for one cycle) starting on the next negative edge of the clock?

BTW, is there any book that teaches these kinds of things? I know the concepts and syntax as well as differences between simulation and sythesizable code, but would love to find best practices for things like the above, or for dealing with logic that have different clock domains.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Can you post the code you have so far? It's a little tricky to visualize what you're doing.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Can you post the code you have so far? It's a little tricky to visualize what you're doing.

    --- Quote End ---

    The goal is to write to the altera megafunction fifo (quartus 11), and I'm trying various ways to do the write request pulse, however the rdempty from the fifo never goes low (i.e. always empty).

    This screenshot :

    https://alteraforum.com/forum/attachment.php?attachmentid=14486&stc=1

    was generated from this code : 

    
wire cmd_push;
reg cmd_push_reg;
always @(negedge clk) begin
    cmd_push_reg <= cmd_push;
end
        
&#8203;fifomf fifomf_inst (    
    .wrclk ( clk ),
    .wrreq ( cmd_push_reg ),
    .data ( 8'h5a ),
    .rdempty ( tp1 )
);    
&#8203;

    I was thinking the clock edges and wrreq must be wrong.. or it's in reset.. but the megafunction code created by quartus doesn't expose reset so my guess that's probably not it 

    
module fifomf (
    data,
    rdclk,
    rdreq,
    wrclk,
    wrreq,
    q,
    rdempty);
    input      data;
    input      rdclk;
    input      rdreq;
    input      wrclk;
    input      wrreq;
    output      q;
    output      rdempty;
    wire  sub_wire0;
    wire  sub_wire1;
    wire  q = sub_wire0;
    wire  rdempty = sub_wire1;
    dcfifo    dcfifo_component (
                .data (data),
                .rdclk (rdclk),
                .rdreq (rdreq),
                .wrclk (wrclk),
                .wrreq (wrreq),
                .q (sub_wire0),
                .rdempty (sub_wire1),
                .aclr (),
                .rdfull (),
                .rdusedw (),
                .wrempty (),
                .wrfull (),
                .wrusedw ());
    defparam
        dcfifo_component.intended_device_family = "Stratix III",
        dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
        dcfifo_component.lpm_numwords = 1024,
        dcfifo_component.lpm_showahead = "OFF",
        dcfifo_component.lpm_type = "dcfifo",
        dcfifo_component.lpm_width = 8,
        dcfifo_component.lpm_widthu = 10,
        dcfifo_component.overflow_checking = "ON",
        dcfifo_component.rdsync_delaypipe = 5,
        dcfifo_component.underflow_checking = "ON",
        dcfifo_component.use_eab = "ON",
        dcfifo_component.wrsync_delaypipe = 5;
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I have done this before to delay a signal from being generated in a rising edge clocked domain to a falling edge clocked domain: 

    
reg rising;
reg falling;
always @(posedge clk)
    begin
    rising <= ~rising;
    end
always @(negedge clk)
    begin
    falling <= rising;
    end

    then rising is a signal that can be used in a rising edge clocked domain; and falling is that same signal delayed by half a clock cycle, suitable for use in a falling edge clocked domain.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The rdclk is disconnected, hence rdempty is always high as it powers up in this state. You need a clock on the read side for any read status signals to do anything.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    I have done this before to delay a signal from being generated in a rising edge clocked domain to a falling edge clocked domain: 

    
reg rising;
reg falling;
always @(posedge clk)
    begin
    rising <= ~rising;
    end
always @(negedge clk)
    begin
    falling <= rising;
    end

    then rising is a signal that can be used in a rising edge clocked domain; and falling is that same signal delayed by half a clock cycle, suitable for use in a falling edge clocked domain.

    --- Quote End ---

    Thanks, exactly what I was looking for!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Thanks you're right! I was thinking it would be a good approach to make sure the write was working before moving on the read but looks like I didn't think about the rdempty/rdclk dependency!