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Altera_Forum's avatar
Altera_Forum
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8 years ago

How to create a neg-edge Write pulse, from a pos-edge Write pulse?

I have a active-high signal that transitions on the positive edge of its clock when it has data ready to be written to memory. I also have ram memory (uses same clock) but expects the write ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I have done this before to delay a signal from being generated in a rising edge clocked domain to a falling edge clocked domain: 


reg rising;
reg falling;
always @(posedge clk)
    begin
    rising <= ~rising;
    end
always @(negedge clk)
    begin
    falling <= rising;
    end

then rising is a signal that can be used in a rising edge clocked domain; and falling is that same signal delayed by half a clock cycle, suitable for use in a falling edge clocked domain.