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Honored Contributor
Honored ContributorHow to create a neg-edge Write pulse, from a pos-edge Write pulse?
I have a active-high signal that transitions on the positive edge of its clock when it has data ready to be written to memory. I also have ram memory (uses same clock) but expects the write ...
Altera_ForumHonored Contributor
Honored ContributorI have done this before to delay a signal from being generated in a rising edge clocked domain to a falling edge clocked domain:
reg rising;
reg falling;
always @(posedge clk)
begin
rising <= ~rising;
end
always @(negedge clk)
begin
falling <= rising;
end
