Honored ContributorI've tried to answer a number of TimeQuest questions here, and as part of that, put together a TimeQuest User Guide. It's on the altera wiki site:
http://alterawiki.com/wiki/timequest_user_guide The first section, Getting Started, is probably the most useful for helping new users get up to speed(or old users have a better idea what they're doing). Anyway, hope it can help someone.
Honored ContributorMinor nit: "the affects of" should be "the effects of"
Honored ContributorVery interesting read! I was thinking that the wiki would be a nice place to hold example of sdc constraints for some standard interfaces too.
Honored ContributorVery much thank you.
It is a wonderful idea now that the Classic Timing Analyzer is no more available.Honored ContributorQuite a few affects/effects errors. Hopefully have them fixed for the next release. I know that can be annoying.
I believe someone else is working on a ton of examples, which is why I stayed away from them, but plan on adding a few that reference the prior material, more as a walk-through. I'm hoping this can be used to lay the groundwork, and understanding that it's easier to look at examples and understand what's going on. (I find a lot of the examples already floating around confuse user's because they don't know the groundwork, but it's far too complicated to take every example and explain everything from the ground up.)Honored Contributor> Contact: ...if there is anything ambiguous, incorrect, or missing, please contact me via ...alteraforum..., sending an email to user Rysc.
Note forum restriction preventing this: "To be able to send e-mails to other users your post count must be 10 or greater." Therefore I will post this way regarding the Report Datasheet section; note [insertions] and /d/e/l/e/t/i/o/n/s/ below: * "values like Tsu, Th and Tco make sense in many I/O cases, but there are a number of situations where they can’t do complete analysis(such as source-synchronous interfaces)". What analysis is available vs missing for souce-synchronous interfaces... specifically, does it report Tco from active edge of clock output to data output? If so, how from the report's Rise and Fall columns? * Clock inversion, "So if two signals['] output ports were clocked on opposite edges of the clock, their data would come out at very different times, but their Clock to Output values would be the same. Luckily, the Datasheet has a column called Clock Edge. The following screenshot is from a design with an output bus called tx_[data]/o/u/t[7:0]..." * PLL Phase-shifts, "Let’s start with the same example as above, whereby a clock with a 20ns period clocks data out and it takes 7ns. Let’s say that it’s going through a PLL now, so the Clock to Output time is /s/t/i/l/l/ 4ns." Assuming 4ns is 7ns with PLL -3ns shift? * "If the user phase-shifts the clock +180 degrees [or]/o/f/ -180 degrees, the data will come out at the exact same time, but the +180 degree shift will give a Clock to Output time of 14ns and the -180 degree phase-shift will give a Clock to Output time of -6ns."
