How to create a neg-edge Write pulse, from a pos-edge Write pulse?

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Can you post the code you have so far? It's a little tricky to visualize what you're doing.

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The goal is to write to the altera megafunction fifo (quartus 11), and I'm trying various ways to do the write request pulse, however the rdempty from the fifo never goes low (i.e. always empty).

This screenshot :

https://alteraforum.com/forum/attachment.php?attachmentid=14486&stc=1

was generated from this code :

wire cmd_push;
reg cmd_push_reg;
always @(negedge clk) begin
    cmd_push_reg <= cmd_push;
end
        
&#8203;fifomf fifomf_inst (    
    .wrclk ( clk ),
    .wrreq ( cmd_push_reg ),
    .data ( 8'h5a ),
    .rdempty ( tp1 )
);    
&#8203;

I was thinking the clock edges and wrreq must be wrong.. or it's in reset.. but the megafunction code created by quartus doesn't expose reset so my guess that's probably not it

module fifomf (
    data,
    rdclk,
    rdreq,
    wrclk,
    wrreq,
    q,
    rdempty);
    input      data;
    input      rdclk;
    input      rdreq;
    input      wrclk;
    input      wrreq;
    output      q;
    output      rdempty;
    wire  sub_wire0;
    wire  sub_wire1;
    wire  q = sub_wire0;
    wire  rdempty = sub_wire1;
    dcfifo    dcfifo_component (
                .data (data),
                .rdclk (rdclk),
                .rdreq (rdreq),
                .wrclk (wrclk),
                .wrreq (wrreq),
                .q (sub_wire0),
                .rdempty (sub_wire1),
                .aclr (),
                .rdfull (),
                .rdusedw (),
                .wrempty (),
                .wrfull (),
                .wrusedw ());
    defparam
        dcfifo_component.intended_device_family = "Stratix III",
        dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
        dcfifo_component.lpm_numwords = 1024,
        dcfifo_component.lpm_showahead = "OFF",
        dcfifo_component.lpm_type = "dcfifo",
        dcfifo_component.lpm_width = 8,
        dcfifo_component.lpm_widthu = 10,
        dcfifo_component.overflow_checking = "ON",
        dcfifo_component.rdsync_delaypipe = 5,
        dcfifo_component.underflow_checking = "ON",
        dcfifo_component.use_eab = "ON",
        dcfifo_component.wrsync_delaypipe = 5;
endmodule