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Altera_Forum
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8 years ago

How to create a neg-edge Write pulse, from a pos-edge Write pulse?

I have a active-high signal that transitions on the positive edge of its clock when it has data ready to be written to memory. I also have ram memory (uses same clock) but expects the write ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The rdclk is disconnected, hence rdempty is always high as it powers up in this state. You need a clock on the read side for any read status signals to do anything.