Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to create a neg-edge Write pulse, from a pos-edge Write pulse?
I have a active-high signal that transitions on the positive edge of its clock when it has data ready to be written to memory. I also have ram memory (uses same clock) but expects the write ...
Altera_ForumHonored Contributor
Honored ContributorThanks you're right! I was thinking it would be a good approach to make sure the write was working before moving on the read but looks like I didn't think about the rdempty/rdclk dependency!
