How do I identify carry/overflow condition in Verilog?

Question

Hi

I need to identify an overflow condition for a counter in Verilog code.

Say that count register is 16bits wide; I make the assignment

count <= count + 1

and I need to know when the overflow condition happens.

I now defined count as 17bits wide and I simply check when 17th bit toggles, and the design works.

Anyway, I think there should be a better and more efficient way to do it.

I have only minor experience with Verilog, so I don't know how to get the overflow status signal from the adder for a generic operation count<=count+n

Cris

altera_forum · Answer

--- Quote Start ---  I now defined count as 17bits wide and I simply check when 17th bit toggles, and the design works. Anyway, I think there should be a better and more efficient way to do it.  --- Quote End ---   Yes, you are writing behavioral code, so you should do the same for the overflow. You are also "allowed" to add the reset on overwflow action for clarity, although it's performed automatically without coding it. if (count == 16'hffff)
begin
  count &lt;= 0;
  // do something on overflow
end The point is to let the design compiler decide how the overflow action can be implemented with least effort. If you want to know how, inspect the gate level code.

altera_forum · Answer

Hi FvM,

What you say was already clear to me. Testing the condition count==16'hffff is good for a simple counter with 1 increments.

But I need to identify overflow for the general case with a n increment, where the counter doesn't hit the ffff value.

I wondered if a Verilog instruction was available, without need to inspect at gate level.

Cris

altera_forum · Answer

Your method of adding 17th bit is the most efficient for modulo 2 counter.

If you mean how to continue counting at overflow for any counter then your example will work for modulo 2 counter. for non modulo 2 you can use variable to predetect overflow and take action:

e.g to count 0:99

clked process

variable : count_v ...

begin

if count_v > 99 then

count_v := countv -99;

else

count_v := count_v + incr;

end if;

count <= count_v;

..

altera_forum · Answer

I don't understand, what you mean with the general overflow condition in contrast to the above example. In behavioral code (count <= count +1), the overflow condition would be always expressed in a similar way, e.g.

if (count >=12345)

altera_forum · Answer

I explain better.

Increment can be 1 or any other value and it changes during circuit operation.

The count is modulo 2. I don't care the actual count value but I must generate a pulse every time the count overflows.

Example 1

old count: 0x4000

increment: 0x0600

new count: 0x4600

no pulse generated

Example 2

old count: 0xFF00

increment: 0x0600

new count: 0x0500

pulse generated

I think this is what kaz correctly understood. So, according to him my bit17 trick is already the best way to do the job.

As I said before I'm not a HDL expert and I always used schematics or gate level design, so I was accustomed with using the overflow/carry signal from the adder. I supposed I could access it from Verilog, too. Probably this is not possible in a pre-synthesis phase.

Thank you both for your answers

Cris

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How do I identify carry/overflow condition in Verilog?

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