How do I identify carry/overflow condition in Verilog?

I agree with the OP. It can be said that it is, in a way, some sort of limitation of the HDL. The OP is right that for using the carry out outside the counter/adder itself, you implement a dummy extra bit as a full counter. Hardware wise, an extra bit would represent an extra LE that it would be wasted.

In an ideal world, the compiler might be able to identify that this extra bit is dummy, that only the carry out is needed, and optimize accordingly. In practice, compilers aren't, yet, that smart.

Thing are complicated in an FPGA, because the carry out signal is usually available at the carry chain only. This means that it is not so easy to optimize and avoid the extra dummy bit. If you insist, it might be possible to perform manual optimization and save one LE. That would probable require using low level WYSIWYG primitives.