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Altera_Forum
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15 years ago

How do I identify carry/overflow condition in Verilog?

Hi I need to identify an overflow condition for a counter in Verilog code. Say that count register is 16bits wide; I make the assignment count <= count + 1 and I need to know when the ove...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi FvM,

What you say was already clear to me. Testing the condition count==16'hffff is good for a simple counter with 1 increments.

But I need to identify overflow for the general case with a n increment, where the counter doesn't hit the ffff value.

I wondered if a Verilog instruction was available, without need to inspect at gate level.

Cris