How do I identify carry/overflow condition in Verilog?

The problem is, that you originally referred to a counter but are actually using an adder. The condition you are asking for is the carry bit of the adder. In this case, I agree, that the 17 th dummy bit is an appropriate way to implement the overflow check. Checking for the MSB toggling to zero would be another option. Most likely they end up in the same gate level code.