How do I identify carry/overflow condition in Verilog?

Your method of adding 17th bit is the most efficient for modulo 2 counter.

If you mean how to continue counting at overflow for any counter then your example will work for modulo 2 counter. for non modulo 2 you can use variable to predetect overflow and take action:

e.g to count 0:99

clked process

variable : count_v ...

begin

if count_v > 99 then

count_v := countv -99;

else

count_v := count_v + incr;

end if;

count <= count_v;

..