Honored Contributor
Honored ContributorI explain better.
Increment can be 1 or any other value and it changes during circuit operation. The count is modulo 2. I don't care the actual count value but I must generate a pulse every time the count overflows. Example 1 old count: 0x4000 increment: 0x0600 new count: 0x4600 no pulse generated Example 2 old count: 0xFF00 increment: 0x0600 new count: 0x0500 pulse generated I think this is what kaz correctly understood. So, according to him my bit17 trick is already the best way to do the job. As I said before I'm not a HDL expert and I always used schematics or gate level design, so I was accustomed with using the overflow/carry signal from the adder. I supposed I could access it from Verilog, too. Probably this is not possible in a pre-synthesis phase. Thank you both for your answers Cris
