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AKohl3's avatar
AKohl3
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6 years ago
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Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.

From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    6 years ago

    Hello there ,

    Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

    As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

    In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

    Hope helps ,

    Thank you ,

    Regards,

    Sree

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  • AKohl3's avatar
    AKohl3
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    6 years ago

    I hope this is not a Quartus standard versus lite issue?

  • AKohl3's avatar
    AKohl3
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    6 years ago

    And if the issue is not software related, can you send me the above depicted correctly compiled project+project files from your end?

    • AKohl3's avatar
      AKohl3
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      6 years ago

      Hi,

      This is a project created by a blogger 'maximator' which once I edit to my design plans removes the ADC block for some reason. Can you send the project file specific to this query, please?

      • SreekumarR_G_Intel's avatar
        SreekumarR_G_Intel
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        6 years ago

        I dont get you . I modified the project file which you sent to me . Please be clear what you really looking for . All the files related to the project file is already there in attachment.

        Thanks ,

        Regards,

        Sree

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
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    6 years ago

    can I know did you get a chance to figure it the issue ? if you still facing the issue kindly let me know ?

    Thank you,

    Regards,

    Sree

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    sorry , didnt see your updated post ; Can I know you still facing the issue ?

    Thank you ,

    Regards,

    Sree

    • AKohl3's avatar
      AKohl3
      Icon for New Contributor rankNew Contributor
      6 years ago

      Yes Sree, I am still facing the same issue besides I have attached all files you requested in the past. Can you please provide an solution to the above attached project file as soon as possible?

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    sorry, i didnt noticed your reply , can i know is that issue resolved ? kindly let me know if you looking for my design files still.

    Apologize my delay in response.

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
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    6 years ago

    Hello , I thought i attached the file to you , Sorry looks i missed out, Can i know you still facing the same issue ? if yes , i will look at again .

    • AKohl3's avatar
      AKohl3
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi,

      I am still facing the same problem. I have been able to check the ADC input if I invoke the Jtag avalon adapter but if I use just the ADC control core the response data is stuck at zero. In the attached project I am trying a simple led blink check using the output of the ADC module. I would really appreciate a prompt reply.

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hello there ,

    Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

    As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

    In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

    Hope helps ,

    Thank you ,

    Regards,

    Sree

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    hello ,

    sorry , I completed missed that your case here.

    can you let me know you still facing the same issue , if yes I can attach the design which another customer posted the same in fourm.

    Thank you ,

    Regards,

    Sree