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AKohl3's avatar
AKohl3
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6 years ago
Solved

Hi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.

From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!
  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    6 years ago

    Hello there ,

    Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.

    As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.

    In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.

    Hope helps ,

    Thank you ,

    Regards,

    Sree

  • AKohl3's avatar
    AKohl3
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    This is a project created by a blogger 'maximator' which once I edit to my design plans removes the ADC block for some reason. Can you send the project file specific to this query, please?

    • SreekumarR_G_Intel's avatar
      SreekumarR_G_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      I dont get you . I modified the project file which you sent to me . Please be clear what you really looking for . All the files related to the project file is already there in attachment.

      Thanks ,

      Regards,

      Sree

    • AKohl3's avatar
      AKohl3
      Icon for New Contributor rankNew Contributor
      6 years ago

      That is not my project at all! Once I open it in quartus the following screenshot shows the different files similar tot the maximator project I mentioned. Can you please ensure the right project files?

    • SreekumarR_G_Intel's avatar
      SreekumarR_G_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      hmm..Can you attach your project file again (Full project .gar format)?

      Thank you ,

      Regards,

      Sree