alt_sld_fab |

2020.02.21.12:07:13 | Datasheet

Overview

All Components
alt_sld_fab_splitter altera_sld_splitter 18.1
Memory Map

| alt_sld_fab_trfabric
control_0
alt_sld_fab_splitter |
control_0 | 0x00000000

## alt_sld_fab

alt_sld_fab v18.1

## Parameters
DESIGN_HASH | 0d4cf5fccf9cd0495baf
NODE_COUNT | 2
MAX_WIDTH | 44
SETTINGS | {fabric trace dir agent trace_width 8 addr_width 5 read_latency 1 has_readdatavalid 0 prefer_traceid {} clock_rate_clk 50000000 psig d0422792} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 psig 9b67919e}
CLOCKS | {id clock_alias_1} {id {} }
AGENTS |
EP_INFOS | {hpath {ADC:u0|ADC_ADC:adc|ADC_ADC_adc_monitor_internal:adc_monitor_internal|altera_trace_monitor_endpoint_wrapper:trace_endpoint|altera_trace_monitor_endpoint:inst|altera_fabric_endpoint:ep} } {hpath {ADC:u0|ADC_ADC:adc|ADC_ADC_adc_monitor_internal:adc_monitor_internal|altera_trace_adc_monitor_core:core|altera_trace_adc_monitor_capture_interface:capture_interface|altera_trace_adc_monitor_issp:issp|altsource_probe:issp_0} }
MIRROR | 0
TOP_HUB | 1
COMPOSED_SETTINGS | {fabric trace dir agent trace_width 8 addr_width 5 read_latency 1 has_readdatavalid 0 prefer_traceid {} clock clk clock_rate_clk 50000000} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY | MAX10FPGA
AUTO_DEVICE | Unknown
AUTO_DEVICE_SPEEDGRADE | Unknown
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_presplit

altera_super_splitter v18.1

## Parameters
MAX_WIDTH | 44
SEND_WIDTHS | 44 6
RECEIVE_WIDTHS | 41 27
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_splitter

altera_sld_splitter v18.1

alt_sld_fab_presplit | pass | alt_sld_fab_splitter
nodes
alt_sld_fab_trfabric | debug_reset_0
debug_reset_0
control_0
control_0
alt_sld_fab_sldfabric | clock_1
clock_1
node_1
node_1
|  | clk_0 | alt_sld_fab_trfabric
|  | clk
|  | capture_0
|  | capture_0
|  | clk_0 | alt_sld_fab_stfabric
|  | clk
|  | clk_0
|  | clk_0
|  | clk_0 | alt_sld_fab_host_link_jtag
|  | clk

## Parameters
FRAGMENTS | {{name clk type clock dir start ports { {clk clk out 1 0} } properties { {clockRate {50000000} } {clockRateKnown {1} } } } {name debug_reset type reset dir end ports { {reset reset in 1 0} } clock clk } {name capture type avalon_streaming dir start ports { {capture_ready ready in 1 1} {capture_valid valid out 1 1} {capture_data data out 8 2} {capture_startofpacket startofpacket out 1 10} {capture_endofpacket endofpacket out 1 11} } properties { {dataBitsPerSymbol {8} } {readyLatency {0} } } clock clk reset debug_reset assign {debug.controlledBy {link_0} debug.interfaceGroup {associatedControl control_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric trace index 1} } } } {name control type avalon dir end ports { {control_write write in 1 2} {control_read read in 1 3} {control_address address in 5 4} {control_writedata writedata in 32 9} {control_readdata readdata out 32 12} } properties { {addressUnits {WORDS} } {readLatency {1} } } clock clk reset debug_reset } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_1} } moduleassign {debug.virtualInterface.link_1 {debug.endpointLink {fabric sld index 1} } } } }
EXAMPLE |
ADD_INTERFACE_ASGN | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_trfabric

altera_trace_fabric v18.1

alt_sld_fab_splitter | clk_0 | alt_sld_fab_trfabric
clk
capture_0
capture_0
alt_sld_fab_stfabric | reset_0
reset
h2t_0
h2t
|  | debug_reset_0 | alt_sld_fab_splitter
|  | debug_reset_0
|  | control_0
|  | control_0
|  | t2h | alt_sld_fab_stfabric
|  | t2h_0

## Parameters
SETTINGS | {trace_width 8 addr_width 5 read_latency 1 has_readdatavalid 0 prefer_traceid {} clock clk clock_rate_clk 50000000}
TRACE_DATA_WIDTH | 0
MEMSIZE | 32768
EXTMEM_BASE | 0
EXTMEM_SIZE | 1048576
CLOCK_RATE | 50000000
WAKE_UP_MODE | IDLE
PIPELINE_STAGE_ON_ALL_INPUTS | true
PERIODIC_TS_REQ_STARTUP | 0
AUTO_DEVICE_FAMILY | MAX10FPGA
AUTO_DEVICE | Unknown
AUTO_DEVICE_SPEEDGRADE | Unknown
AUTO_CLK_CLOCK_DOMAIN | 5
AUTO_CLK_RESET_DOMAIN | 5
AUTO_STORAGE_MASTER_ADDRESS_MAP |
AUTO_STORAGE_MASTER_ADDRESS_WIDTH | AddressWidth = -1
deviceFamily | MAX 10
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_host_link_jtag

altera_jtag_debug_link_internal v18.1

alt_sld_fab_splitter | clk_0 | alt_sld_fab_host_link_jtag
clk
alt_sld_fab_stfabric | t2h
t2h
alt_sld_fab_sldfabric | clock_0
tck
node_0
node
|  | reset | alt_sld_fab_stfabric
|  | reset
|  | h2t
|  | h2t
|  | mgmt
|  | mgmt

## Parameters
USE_PLI | 0
PLI_PORT | 50000
CHANNEL_WIDTH | 8
EXPORT_JTAG | 1
AUTO_DEVICE_FAMILY | MAX10FPGA
AUTO_DEVICE | Unknown
AUTO_DEVICE_SPEEDGRADE | Unknown
AUTO_CLK_CLOCK_RATE | 50000000
AUTO_CLK_CLOCK_DOMAIN | 5
AUTO_CLK_RESET_DOMAIN | 5
deviceFamily | MAX 10
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_stfabric

altera_debug_fabric v18.1

alt_sld_fab_splitter | clk_0 | alt_sld_fab_stfabric
clk
clk_0
clk_0
alt_sld_fab_host_link_jtag | reset
reset
h2t
h2t
mgmt
mgmt
alt_sld_fab_trfabric | t2h
t2h_0
|  | t2h | alt_sld_fab_host_link_jtag
|  | t2h
|  | reset_0 | alt_sld_fab_trfabric
|  | reset
|  | h2t_0
|  | h2t

## Parameters
STREAMS | 1
USE_ROM | 0
STREAM_CONFIG | {data_width 8 channel_width 1 has_mgmt 0 ready_latency 0 mfr_code 110 type_code 261 prefer_host {} clock clk_0 clock_rate_clk 0}
CHANNEL_WIDTH | 8
AUTO_DEVICE_FAMILY | MAX10FPGA
AUTO_DEVICE | Unknown
AUTO_DEVICE_SPEEDGRADE | Unknown
AUTO_CLK_CLOCK_RATE | 50000000
AUTO_CLK_CLOCK_DOMAIN | 5
AUTO_CLK_RESET_DOMAIN | 5
deviceFamily | MAX 10
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_jtagpins

altera_jtag_pins_bridge v18.1

## Parameters
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_sldfabric

altera_sld_jtag_hub v18.1

alt_sld_fab_jtagpins | clock | alt_sld_fab_sldfabric
clock
node
node
|  | clock_0 | alt_sld_fab_host_link_jtag
|  | tck
|  | node_0
|  | node
|  | clock_1 | alt_sld_fab_splitter
|  | clock_1
|  | node_1
|  | node_1
|  | ident | alt_sld_fab_ident
|  | ident_0

## Parameters
DEVICE_FAMILY | MAX10FPGA
SETTINGS | {mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host JTAG} {mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} }
COUNT | 2
N_SEL_BITS | 2
N_NODE_IR_BITS | 5
NODE_INFO | 0000000001001000011011100000000000001100001000000110111000000000
COMPILATION_MODE | 0
BROADCAST_FEATURE | 1
FORCE_IR_CAPTURE_FEATURE | 1
FORCE_PRE_1_4_FEATURE | 0
NEGEDGE_TDO_LATCH | 1
ENABLE_SOFT_CORE_CONTROLLER | 0
TOP_HUB | 1
CONN_INDEX | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_ident

altera_connection_identification_hub v18.1

alt_sld_fab_sldfabric | ident | alt_sld_fab_ident
ident_0

## Parameters
DESIGN_HASH | 0d4cf5fccf9cd0495baf
COUNT | 1
SETTINGS | {width 4 latency 0}
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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