Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
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u0|rst_controller|alt_rst_req_sync_uq1 | 2 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|rst_controller|alt_rst_sync_uq1 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|rst_controller | 33 | 32 | 0 | 32 | 2 | 32 | 32 | 32 | 0 | 0 | 0 | 0 | 0
u0|pll|sd1 | 3 | 1 | 0 | 1 | 6 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|pll|stdsync2|dffpipe3 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|pll|stdsync2 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|pll | 48 | 48 | 30 | 48 | 41 | 48 | 48 | 48 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|adc_inst|adcblock_instance | 9 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|adc_inst|decoder | 5 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|adc_inst | 9 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr | 4 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count | 4 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram | 28 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw | 5 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo | 16 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated | 16 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm|ts_avrg_fifo | 16 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal|u_control_fsm | 26 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|adc|control_internal | 13 | 1 | 0 | 1 | 21 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|adc | 12 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0 | 10 | 9 | 0 | 9 | 22 | 9 | 9 | 9 | 0 | 0 | 0 | 0 | 0
gp|gpio_inst|gpio_one_bit.i_loop[0].altgpio_bit_i | 11 | 5 | 7 | 5 | 3 | 5 | 5 | 5 | 2 | 0 | 0 | 0 | 0
gp|gpio_inst | 14 | 17 | 0 | 17 | 6 | 17 | 17 | 17 | 2 | 0 | 2 | 0 | 2
gp | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0