
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera;
use altera.altera_primitives_components.all; 

entity led_blink_ADC is
	port (
		P_I_CLK	   			: in std_logic	;
		P_I_CLK_B				: in std_logic ;
		
		P_OUT_LED0				: out std_logic_vector(0 downto 0);   
		P_OUT_LED1				: out std_logic_vector(0 downto 0);
		P_OUT_LED2				: out std_logic_vector(0 downto 0);
		P_OUT_LED3				: out std_logic_vector(0 downto 0);
		P_OUT_LED4				: out std_logic_vector(0 downto 0);
		P_OUT_LED5				: out std_logic_vector(0 downto 0);
		P_OUT_LED6				: out std_logic_vector(0 downto 0);
		P_OUT_LED7				: out std_logic_vector(0 downto 0);
		P_OUT_LED8				: out std_logic_vector(0 downto 0);
		P_OUT_LED9				: out std_logic_vector(0 downto 0);
		P_OUT_LED10				: out std_logic_vector(0 downto 0);
		P_OUT_LED11				: out std_logic_vector(0 downto 0);
		P_OUT_LED12				: out std_logic_vector(0 downto 0);
		P_OUT_LED13				: out std_logic_vector(0 downto 0);
		P_OUT_LED14				: out std_logic_vector(0 downto 0);
		P_OUT_LED15				: out std_logic_vector(0 downto 0);
		
		P_O_LED_1				: out std_logic;
		P_O_LED_2				: out std_logic;
		P_O_LED_3				: out std_logic;
		P_O_LED_4				: out std_logic
		);
	end led_blink_ADC;

architecture data of led_blink_ADC is

	signal clk_100			: std_logic;
	signal clk_100_2     : std_logic;
	signal clk_10        : std_logic;
	signal reset         : std_logic;
	--signal lock          : std_logic;
	signal led           : std_logic;
	
	
	signal command_valid          : std_logic;
	signal command_ch 				: std_logic_vector(4 downto 0);
	signal command_start          : std_logic;
	signal command_stop				: std_logic;
	signal command_ready	    		: std_logic;
	signal response_valid         : std_logic;
	signal response_ch				: std_logic_vector(4 downto 0);
	signal response_start         : std_logic;
	signal response_stop				: std_logic;
	--signal response_empty			: std_logic_vector(0 downto 0);
	signal data				: std_logic_vector(11 downto 0);
	signal reset_n			: std_logic;
	
	
	
	
	component gpio 
	port (
		dout     : out std_logic; --     dout.export
		pad_in   : in  std_logic; --     pad_in.export
		pad_in_b : in  std_logic  --     pad_in_b.export
	);
	end component;
	
	component ADC 
	port (
		adc_command_valid          : in  std_logic                     ;             --  adc_command.valid
		adc_command_channel        : in  std_logic_vector(4 downto 0)  ; --             .channel
		adc_command_startofpacket  : in  std_logic                     ;             --             .startofpacket
		adc_command_endofpacket    : in  std_logic                     ;             --             .endofpacket
		adc_command_ready          : out std_logic;                                        --             .ready
		adc_response_valid         : out std_logic;                            -- adc_response.valid
		adc_response_startofpacket : out std_logic;                            --             .startofpacket
		adc_response_endofpacket   : out std_logic;                            --             .endofpacket
		--adc_response_empty         : out std_logic_vector(0 downto 0);         --             .empty
		adc_response_channel       : out std_logic_vector(4 downto 0);         --             .channel
		adc_response_data          : out std_logic_vector(11 downto 0);        --             .data
		clk_clk                    : in  std_logic                     ; --          clk.clk
		pll_c1_clk                 : out std_logic;                            --       pll_c1.clk
		reset_reset_n              : in  std_logic                       --        reset.reset_n
	);
   end component;
	
	

	
begin



P_OUT_LED4 <=not(response_ch(0 downto 0));
P_OUT_LED5 <=not(response_ch(1 downto 1));
P_OUT_LED6 <=not(response_ch(2 downto 2));
P_OUT_LED7 <=not(response_ch(4 downto 4));


P_O_LED_1  <= '1';
P_O_LED_2  <= '0';
P_O_LED_3  <= '0';
P_O_LED_4  <= led;
reset_n    <= '1';

command_valid <='1';
command_ch    <="00000";


	-- LVDS input to internal signal

	gp: gpio port map (
	dout     => clk_100,
	pad_in   => P_I_CLK,
	pad_in_b => P_I_CLK_B
	);

	u0: ADC port map (
		adc_command_valid              => command_valid,                        -- adc_response.valid
		adc_command_channel            => command_ch,
		adc_command_startofpacket      => command_start,                        --             .startofpacket
		adc_command_endofpacket        => command_stop,                        --             .endofpacket
		adc_command_ready              => command_ready,           --             .empty
		adc_response_valid             => response_valid,                        -- adc_response.valid
		adc_response_startofpacket     => response_start,                        --             .startofpacket
		adc_response_endofpacket       => response_stop,                        --             .endofpacket
		--adc_response_empty             => response_empty,           --             .empty
		adc_response_channel           => response_ch,              --             .channel
		adc_response_data              => data,            --             .data
		clk_clk                        => clk_100,         --          clk.clk
		pll_c1_clk                     => clk_100_2,       --       pll_c1.clk
		reset_reset_n                  => reset_n          --        reset.reset_n
   );

	
	
	proc_reset : process (clk_100_2)
	begin
	if(rising_edge(clk_100_2)) then
			led   <='1';	
	end if;
	end process;
	
	
	proc_data : process(clk_100,command_ready,response_valid,response_start)
	begin
	if(rising_edge(clk_100) and command_ready='1' and response_valid='1' and response_start='1') then
		P_OUT_LED8 <=data(0 downto 0);
		P_OUT_LED9 <=data(1 downto 1);
		P_OUT_LED10 <=data(2 downto 2);
		P_OUT_LED11 <=data(3 downto 3);
		P_OUT_LED12 <=data(4 downto 4);
		P_OUT_LED13 <=data(5 downto 5);
		P_OUT_LED14 <=data(6 downto 6);
		P_OUT_LED15 <=data(7 downto 7);
		P_OUT_LED0 <=data(8 downto 8);
		P_OUT_LED1 <=data(9 downto 9);
		P_OUT_LED2 <=data(10 downto 10);
		P_OUT_LED3 <=data(11 downto 11);
	end if;
	end process;
end data;	
	
