// alt_sld_fab_alt_sld_fab_trfabric.v

// This file was auto-generated from altera_trace_fabric_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module alt_sld_fab_alt_sld_fab_trfabric #(
		parameter WAKE_UP_MODE            = "IDLE",
		parameter PERIODIC_TS_REQ_STARTUP = 0
	) (
		input  wire        clk_clk,                 //           clk.clk
		input  wire        reset_reset,             //         reset.reset
		output wire        debug_reset_reset,       //   debug_reset.reset
		output wire        h2t_ready,               //           h2t.ready
		input  wire        h2t_valid,               //              .valid
		input  wire        h2t_startofpacket,       //              .startofpacket
		input  wire        h2t_endofpacket,         //              .endofpacket
		input  wire [7:0]  h2t_data,                //              .data
		input  wire [0:0]  h2t_channel,             //              .channel
		input  wire        t2h_ready,               //           t2h.ready
		output wire        t2h_valid,               //              .valid
		output wire        t2h_startofpacket,       //              .startofpacket
		output wire        t2h_endofpacket,         //              .endofpacket
		output wire [7:0]  t2h_data,                //              .data
		output wire [0:0]  t2h_channel,             //              .channel
		output wire        capture_0_ready,         //     capture_0.ready
		input  wire        capture_0_valid,         //              .valid
		input  wire [7:0]  capture_0_data,          //              .data
		input  wire        capture_0_startofpacket, //              .startofpacket
		input  wire        capture_0_endofpacket,   //              .endofpacket
		output wire        control_0_write,         //     control_0.write
		output wire        control_0_read,          //              .read
		output wire [4:0]  control_0_address,       //              .address
		output wire [31:0] control_0_writedata,     //              .writedata
		input  wire [31:0] control_0_readdata,      //              .readdata
		output wire        debug_reset_0_reset      // debug_reset_0.reset
	);

	wire         h2t_pipeline_source0_valid;                    // h2t_pipeline:out_valid -> demux:in_valid
	wire   [7:0] h2t_pipeline_source0_data;                     // h2t_pipeline:out_data -> demux:in_data
	wire         h2t_pipeline_source0_ready;                    // demux:in_ready -> h2t_pipeline:out_ready
	wire   [0:0] h2t_pipeline_source0_channel;                  // h2t_pipeline:out_channel -> demux:in_channel
	wire         h2t_pipeline_source0_startofpacket;            // h2t_pipeline:out_startofpacket -> demux:in_startofpacket
	wire         h2t_pipeline_source0_endofpacket;              // h2t_pipeline:out_endofpacket -> demux:in_endofpacket
	wire         mux_out_valid;                                 // mux:out_valid -> t2h_pipeline:in_valid
	wire   [7:0] mux_out_data;                                  // mux:out_data -> t2h_pipeline:in_data
	wire         mux_out_ready;                                 // t2h_pipeline:in_ready -> mux:out_ready
	wire         mux_out_channel;                               // mux:out_channel -> t2h_pipeline:in_channel
	wire         mux_out_startofpacket;                         // mux:out_startofpacket -> t2h_pipeline:in_startofpacket
	wire         mux_out_endofpacket;                           // mux:out_endofpacket -> t2h_pipeline:in_endofpacket
	wire         demux_out0_valid;                              // demux:out0_valid -> trans0:dbg_in_valid
	wire   [7:0] demux_out0_data;                               // demux:out0_data -> trans0:dbg_in_data
	wire         demux_out0_ready;                              // trans0:dbg_in_ready -> demux:out0_ready
	wire         demux_out0_startofpacket;                      // demux:out0_startofpacket -> trans0:dbg_in_sop
	wire         demux_out0_endofpacket;                        // demux:out0_endofpacket -> trans0:dbg_in_eop
	wire         trans0_t2h_valid;                              // trans0:dbg_out_valid -> mux:in0_valid
	wire   [7:0] trans0_t2h_data;                               // trans0:dbg_out_data -> mux:in0_data
	wire         trans0_t2h_ready;                              // mux:in0_ready -> trans0:dbg_out_ready
	wire         trans0_t2h_startofpacket;                      // trans0:dbg_out_sop -> mux:in0_startofpacket
	wire         trans0_t2h_endofpacket;                        // trans0:dbg_out_eop -> mux:in0_endofpacket
	wire         capture_t2h_valid;                             // capture:dbg_out_valid -> wide_capture_pipeline:in_valid
	wire  [31:0] capture_t2h_data;                              // capture:dbg_out_data -> wide_capture_pipeline:in_data
	wire         capture_t2h_ready;                             // wide_capture_pipeline:in_ready -> capture:dbg_out_ready
	wire         capture_t2h_startofpacket;                     // capture:dbg_out_sop -> wide_capture_pipeline:in_startofpacket
	wire         capture_t2h_endofpacket;                       // capture:dbg_out_eop -> wide_capture_pipeline:in_endofpacket
	wire   [1:0] capture_t2h_empty;                             // capture:dbg_out_empty -> wide_capture_pipeline:in_empty
	wire         wide_capture_pipeline_source0_valid;           // wide_capture_pipeline:out_valid -> capture_width:in_valid
	wire  [31:0] wide_capture_pipeline_source0_data;            // wide_capture_pipeline:out_data -> capture_width:in_data
	wire         wide_capture_pipeline_source0_ready;           // capture_width:in_ready -> wide_capture_pipeline:out_ready
	wire         wide_capture_pipeline_source0_startofpacket;   // wide_capture_pipeline:out_startofpacket -> capture_width:in_startofpacket
	wire         wide_capture_pipeline_source0_endofpacket;     // wide_capture_pipeline:out_endofpacket -> capture_width:in_endofpacket
	wire   [1:0] wide_capture_pipeline_source0_empty;           // wide_capture_pipeline:out_empty -> capture_width:in_empty
	wire         capture_width_out_valid;                       // capture_width:out_valid -> capture_pipeline:in_valid
	wire   [7:0] capture_width_out_data;                        // capture_width:out_data -> capture_pipeline:in_data
	wire         capture_width_out_ready;                       // capture_pipeline:in_ready -> capture_width:out_ready
	wire         capture_width_out_startofpacket;               // capture_width:out_startofpacket -> capture_pipeline:in_startofpacket
	wire         capture_width_out_endofpacket;                 // capture_width:out_endofpacket -> capture_pipeline:in_endofpacket
	wire         capture_pipeline_source0_valid;                // capture_pipeline:out_valid -> mux:in1_valid
	wire   [7:0] capture_pipeline_source0_data;                 // capture_pipeline:out_data -> mux:in1_data
	wire         capture_pipeline_source0_ready;                // mux:in1_ready -> capture_pipeline:out_ready
	wire         capture_pipeline_source0_startofpacket;        // capture_pipeline:out_startofpacket -> mux:in1_startofpacket
	wire         capture_pipeline_source0_endofpacket;          // capture_pipeline:out_endofpacket -> mux:in1_endofpacket
	wire         capture_pipe_source0_valid;                    // capture_pipe:out_valid -> capture:trace_packet_valid
	wire  [31:0] capture_pipe_source0_data;                     // capture_pipe:out_data -> capture:trace_packet_data
	wire         capture_pipe_source0_ready;                    // capture:trace_packet_ready -> capture_pipe:out_ready
	wire   [0:0] capture_pipe_source0_channel;                  // capture_pipe:out_channel -> capture:trace_packet_chnl
	wire         capture_pipe_source0_startofpacket;            // capture_pipe:out_startofpacket -> capture:trace_packet_sop
	wire         capture_pipe_source0_endofpacket;              // capture_pipe:out_endofpacket -> capture:trace_packet_eop
	wire   [1:0] capture_pipe_source0_empty;                    // capture_pipe:out_empty -> capture:trace_packet_empty
	wire         capture_remap_out_valid;                       // capture_remap:out_valid -> capture_pipe:in_valid
	wire  [31:0] capture_remap_out_data;                        // capture_remap:out_data -> capture_pipe:in_data
	wire         capture_remap_out_ready;                       // capture_pipe:in_ready -> capture_remap:out_ready
	wire   [0:0] capture_remap_out_channel;                     // capture_remap:out_channel -> capture_pipe:in_channel
	wire         capture_remap_out_startofpacket;               // capture_remap:out_startofpacket -> capture_pipe:in_startofpacket
	wire         capture_remap_out_endofpacket;                 // capture_remap:out_endofpacket -> capture_pipe:in_endofpacket
	wire   [1:0] capture_remap_out_empty;                       // capture_remap:out_empty -> capture_pipe:in_empty
	wire         capture_mux0_out_valid;                        // capture_mux0:out_valid -> capture_remap:in_valid
	wire  [31:0] capture_mux0_out_data;                         // capture_mux0:out_data -> capture_remap:in_data
	wire         capture_mux0_out_ready;                        // capture_remap:in_ready -> capture_mux0:out_ready
	wire         capture_mux0_out_channel;                      // capture_mux0:out_channel -> capture_remap:in_channel
	wire         capture_mux0_out_startofpacket;                // capture_mux0:out_startofpacket -> capture_remap:in_startofpacket
	wire         capture_mux0_out_endofpacket;                  // capture_mux0:out_endofpacket -> capture_remap:in_endofpacket
	wire   [1:0] capture_mux0_out_empty;                        // capture_mux0:out_empty -> capture_remap:in_empty
	wire         capture_st_sync_req_clk_clk;                   // capture:async_ts_sync_clk -> sync0:async_ts_sync_clk
	wire         sync0_capture_valid;                           // sync0:av_st_tr_valid -> sync_pipe0:in_valid
	wire  [31:0] sync0_capture_data;                            // sync0:av_st_tr_data -> sync_pipe0:in_data
	wire         sync0_capture_ready;                           // sync_pipe0:in_ready -> sync0:av_st_tr_ready
	wire         sync0_capture_startofpacket;                   // sync0:av_st_tr_sop -> sync_pipe0:in_startofpacket
	wire         sync0_capture_endofpacket;                     // sync0:av_st_tr_eop -> sync_pipe0:in_endofpacket
	wire   [1:0] sync0_capture_empty;                           // sync0:av_st_tr_empty -> sync_pipe0:in_empty
	wire         sync_pipe0_source0_valid;                      // sync_pipe0:out_valid -> capture_mux0:in0_valid
	wire  [31:0] sync_pipe0_source0_data;                       // sync_pipe0:out_data -> capture_mux0:in0_data
	wire         sync_pipe0_source0_ready;                      // capture_mux0:in0_ready -> sync_pipe0:out_ready
	wire         sync_pipe0_source0_startofpacket;              // sync_pipe0:out_startofpacket -> capture_mux0:in0_startofpacket
	wire         sync_pipe0_source0_endofpacket;                // sync_pipe0:out_endofpacket -> capture_mux0:in0_endofpacket
	wire   [1:0] sync_pipe0_source0_empty;                      // sync_pipe0:out_empty -> capture_mux0:in0_empty
	wire         capture_pipe0_1_source0_valid;                 // capture_pipe0_1:out_valid -> capture_mux0:in1_valid
	wire  [31:0] capture_pipe0_1_source0_data;                  // capture_pipe0_1:out_data -> capture_mux0:in1_data
	wire         capture_pipe0_1_source0_ready;                 // capture_mux0:in1_ready -> capture_pipe0_1:out_ready
	wire         capture_pipe0_1_source0_startofpacket;         // capture_pipe0_1:out_startofpacket -> capture_mux0:in1_startofpacket
	wire         capture_pipe0_1_source0_endofpacket;           // capture_pipe0_1:out_endofpacket -> capture_mux0:in1_endofpacket
	wire   [1:0] capture_pipe0_1_source0_empty;                 // capture_pipe0_1:out_empty -> capture_mux0:in1_empty
	wire         trans0_master_waitrequest;                     // mm_interconnect_0:trans0_master_waitrequest -> trans0:master_waitrequest
	wire  [31:0] trans0_master_readdata;                        // mm_interconnect_0:trans0_master_readdata -> trans0:master_readdata
	wire         trans0_master_read;                            // trans0:master_read -> mm_interconnect_0:trans0_master_read
	wire   [7:0] trans0_master_address;                         // trans0:master_address -> mm_interconnect_0:trans0_master_address
	wire         trans0_master_readdatavalid;                   // mm_interconnect_0:trans0_master_readdatavalid -> trans0:master_read_data_valid
	wire         trans0_master_write;                           // trans0:master_write -> mm_interconnect_0:trans0_master_write
	wire  [31:0] trans0_master_writedata;                       // trans0:master_write_data -> mm_interconnect_0:trans0_master_writedata
	wire  [31:0] mm_interconnect_0_rom_rom_readdata;            // rom:rom_readdata -> mm_interconnect_0:rom_rom_readdata
	wire   [2:0] mm_interconnect_0_rom_rom_address;             // mm_interconnect_0:rom_rom_address -> rom:rom_address
	wire         mm_interconnect_0_rom_rom_read;                // mm_interconnect_0:rom_rom_read -> rom:rom_read
	wire  [31:0] mm_interconnect_0_capture_csr_slave_readdata;  // capture:csr_s_readdata -> mm_interconnect_0:capture_csr_slave_readdata
	wire   [5:0] mm_interconnect_0_capture_csr_slave_address;   // mm_interconnect_0:capture_csr_slave_address -> capture:csr_s_address
	wire         mm_interconnect_0_capture_csr_slave_read;      // mm_interconnect_0:capture_csr_slave_read -> capture:csr_s_read
	wire         mm_interconnect_0_capture_csr_slave_write;     // mm_interconnect_0:capture_csr_slave_write -> capture:csr_s_write
	wire  [31:0] mm_interconnect_0_capture_csr_slave_writedata; // mm_interconnect_0:capture_csr_slave_writedata -> capture:csr_s_write_data
	wire  [31:0] mm_interconnect_0_bridge_0_s0_readdata;        // bridge_0:s0_readdata -> mm_interconnect_0:bridge_0_s0_readdata
	wire         mm_interconnect_0_bridge_0_s0_waitrequest;     // bridge_0:s0_waitrequest -> mm_interconnect_0:bridge_0_s0_waitrequest
	wire         mm_interconnect_0_bridge_0_s0_debugaccess;     // mm_interconnect_0:bridge_0_s0_debugaccess -> bridge_0:s0_debugaccess
	wire   [6:0] mm_interconnect_0_bridge_0_s0_address;         // mm_interconnect_0:bridge_0_s0_address -> bridge_0:s0_address
	wire         mm_interconnect_0_bridge_0_s0_read;            // mm_interconnect_0:bridge_0_s0_read -> bridge_0:s0_read
	wire   [3:0] mm_interconnect_0_bridge_0_s0_byteenable;      // mm_interconnect_0:bridge_0_s0_byteenable -> bridge_0:s0_byteenable
	wire         mm_interconnect_0_bridge_0_s0_readdatavalid;   // bridge_0:s0_readdatavalid -> mm_interconnect_0:bridge_0_s0_readdatavalid
	wire         mm_interconnect_0_bridge_0_s0_write;           // mm_interconnect_0:bridge_0_s0_write -> bridge_0:s0_write
	wire  [31:0] mm_interconnect_0_bridge_0_s0_writedata;       // mm_interconnect_0:bridge_0_s0_writedata -> bridge_0:s0_writedata
	wire   [0:0] mm_interconnect_0_bridge_0_s0_burstcount;      // mm_interconnect_0:bridge_0_s0_burstcount -> bridge_0:s0_burstcount
	wire         capture_storage_mm_master_waitrequest;         // mm_interconnect_1:capture_storage_mm_master_waitrequest -> capture:stg_m_waitrequest
	wire  [31:0] capture_storage_mm_master_readdata;            // mm_interconnect_1:capture_storage_mm_master_readdata -> capture:stg_m_readdata
	wire         capture_storage_mm_master_read;                // capture:stg_m_read -> mm_interconnect_1:capture_storage_mm_master_read
	wire  [12:0] capture_storage_mm_master_address;             // capture:stg_m_address -> mm_interconnect_1:capture_storage_mm_master_address
	wire         capture_storage_mm_master_readdatavalid;       // mm_interconnect_1:capture_storage_mm_master_readdatavalid -> capture:stg_m_read_data_valid
	wire         capture_storage_mm_master_write;               // capture:stg_m_write -> mm_interconnect_1:capture_storage_mm_master_write
	wire  [31:0] capture_storage_mm_master_writedata;           // capture:stg_m_write_data -> mm_interconnect_1:capture_storage_mm_master_writedata
	wire         mm_interconnect_1_mem_s1_chipselect;           // mm_interconnect_1:mem_s1_chipselect -> mem:chipselect
	wire  [31:0] mm_interconnect_1_mem_s1_readdata;             // mem:readdata -> mm_interconnect_1:mem_s1_readdata
	wire  [12:0] mm_interconnect_1_mem_s1_address;              // mm_interconnect_1:mem_s1_address -> mem:address
	wire   [3:0] mm_interconnect_1_mem_s1_byteenable;           // mm_interconnect_1:mem_s1_byteenable -> mem:byteenable
	wire         mm_interconnect_1_mem_s1_write;                // mm_interconnect_1:mem_s1_write -> mem:write
	wire  [31:0] mm_interconnect_1_mem_s1_writedata;            // mm_interconnect_1:mem_s1_writedata -> mem:writedata
	wire         mm_interconnect_1_mem_s1_clken;                // mm_interconnect_1:mem_s1_clken -> mem:clken
	wire         bridge_0_m0_waitrequest;                       // mm_interconnect_2:bridge_0_m0_waitrequest -> bridge_0:m0_waitrequest
	wire  [31:0] bridge_0_m0_readdata;                          // mm_interconnect_2:bridge_0_m0_readdata -> bridge_0:m0_readdata
	wire         bridge_0_m0_debugaccess;                       // bridge_0:m0_debugaccess -> mm_interconnect_2:bridge_0_m0_debugaccess
	wire   [6:0] bridge_0_m0_address;                           // bridge_0:m0_address -> mm_interconnect_2:bridge_0_m0_address
	wire         bridge_0_m0_read;                              // bridge_0:m0_read -> mm_interconnect_2:bridge_0_m0_read
	wire   [3:0] bridge_0_m0_byteenable;                        // bridge_0:m0_byteenable -> mm_interconnect_2:bridge_0_m0_byteenable
	wire         bridge_0_m0_readdatavalid;                     // mm_interconnect_2:bridge_0_m0_readdatavalid -> bridge_0:m0_readdatavalid
	wire  [31:0] bridge_0_m0_writedata;                         // bridge_0:m0_writedata -> mm_interconnect_2:bridge_0_m0_writedata
	wire         bridge_0_m0_write;                             // bridge_0:m0_write -> mm_interconnect_2:bridge_0_m0_write
	wire   [0:0] bridge_0_m0_burstcount;                        // bridge_0:m0_burstcount -> mm_interconnect_2:bridge_0_m0_burstcount
	wire         avalon_st_adapter_out_0_valid;                 // avalon_st_adapter:out_0_valid -> capture_pipe0_1:in_valid
	wire  [31:0] avalon_st_adapter_out_0_data;                  // avalon_st_adapter:out_0_data -> capture_pipe0_1:in_data
	wire         avalon_st_adapter_out_0_ready;                 // capture_pipe0_1:in_ready -> avalon_st_adapter:out_0_ready
	wire         avalon_st_adapter_out_0_startofpacket;         // avalon_st_adapter:out_0_startofpacket -> capture_pipe0_1:in_startofpacket
	wire         avalon_st_adapter_out_0_endofpacket;           // avalon_st_adapter:out_0_endofpacket -> capture_pipe0_1:in_endofpacket
	wire   [1:0] avalon_st_adapter_out_0_empty;                 // avalon_st_adapter:out_0_empty -> capture_pipe0_1:in_empty
	wire         rst_controller_reset_out_reset_req;            // rst_controller:reset_req -> [mem:reset_req, rst_translator:reset_req_in]

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (WAKE_UP_MODE != "IDLE")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					wake_up_mode_check ( .error(1'b1) );
		end
		if (PERIODIC_TS_REQ_STARTUP != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					periodic_ts_req_startup_check ( .error(1'b1) );
		end
	endgenerate

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (1),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) h2t_pipeline (
		.clk               (clk_clk),                            //       cr0.clk
		.reset             (debug_reset_0_reset),                // cr0_reset.reset
		.in_ready          (h2t_ready),                          //     sink0.ready
		.in_valid          (h2t_valid),                          //          .valid
		.in_startofpacket  (h2t_startofpacket),                  //          .startofpacket
		.in_endofpacket    (h2t_endofpacket),                    //          .endofpacket
		.in_data           (h2t_data),                           //          .data
		.in_channel        (h2t_channel),                        //          .channel
		.out_ready         (h2t_pipeline_source0_ready),         //   source0.ready
		.out_valid         (h2t_pipeline_source0_valid),         //          .valid
		.out_startofpacket (h2t_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (h2t_pipeline_source0_endofpacket),   //          .endofpacket
		.out_data          (h2t_pipeline_source0_data),          //          .data
		.out_channel       (h2t_pipeline_source0_channel),       //          .channel
		.in_empty          (1'b0),                               // (terminated)
		.out_empty         (),                                   // (terminated)
		.out_error         (),                                   // (terminated)
		.in_error          (1'b0)                                // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_demux demux (
		.clk                (clk_clk),                            //   clk.clk
		.reset_n            (~debug_reset_0_reset),               // reset.reset_n
		.in_data            (h2t_pipeline_source0_data),          //    in.data
		.in_valid           (h2t_pipeline_source0_valid),         //      .valid
		.in_ready           (h2t_pipeline_source0_ready),         //      .ready
		.in_startofpacket   (h2t_pipeline_source0_startofpacket), //      .startofpacket
		.in_endofpacket     (h2t_pipeline_source0_endofpacket),   //      .endofpacket
		.in_channel         (h2t_pipeline_source0_channel),       //      .channel
		.out0_data          (demux_out0_data),                    //  out0.data
		.out0_valid         (demux_out0_valid),                   //      .valid
		.out0_ready         (demux_out0_ready),                   //      .ready
		.out0_startofpacket (demux_out0_startofpacket),           //      .startofpacket
		.out0_endofpacket   (demux_out0_endofpacket),             //      .endofpacket
		.out1_data          (),                                   //  out1.data
		.out1_valid         (),                                   //      .valid
		.out1_ready         (1'b1),                               //      .ready
		.out1_startofpacket (),                                   //      .startofpacket
		.out1_endofpacket   ()                                    //      .endofpacket
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (1),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) t2h_pipeline (
		.clk               (clk_clk),               //       cr0.clk
		.reset             (debug_reset_0_reset),   // cr0_reset.reset
		.in_ready          (mux_out_ready),         //     sink0.ready
		.in_valid          (mux_out_valid),         //          .valid
		.in_startofpacket  (mux_out_startofpacket), //          .startofpacket
		.in_endofpacket    (mux_out_endofpacket),   //          .endofpacket
		.in_data           (mux_out_data),          //          .data
		.in_channel        (mux_out_channel),       //          .channel
		.out_ready         (t2h_ready),             //   source0.ready
		.out_valid         (t2h_valid),             //          .valid
		.out_startofpacket (t2h_startofpacket),     //          .startofpacket
		.out_endofpacket   (t2h_endofpacket),       //          .endofpacket
		.out_data          (t2h_data),              //          .data
		.out_channel       (t2h_channel),           //          .channel
		.in_empty          (1'b0),                  // (terminated)
		.out_empty         (),                      // (terminated)
		.out_error         (),                      // (terminated)
		.in_error          (1'b0)                   // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_mux mux (
		.clk               (clk_clk),                                //   clk.clk
		.reset_n           (~debug_reset_0_reset),                   // reset.reset_n
		.out_data          (mux_out_data),                           //   out.data
		.out_valid         (mux_out_valid),                          //      .valid
		.out_ready         (mux_out_ready),                          //      .ready
		.out_startofpacket (mux_out_startofpacket),                  //      .startofpacket
		.out_endofpacket   (mux_out_endofpacket),                    //      .endofpacket
		.out_channel       (mux_out_channel),                        //      .channel
		.in0_data          (trans0_t2h_data),                        //   in0.data
		.in0_valid         (trans0_t2h_valid),                       //      .valid
		.in0_ready         (trans0_t2h_ready),                       //      .ready
		.in0_startofpacket (trans0_t2h_startofpacket),               //      .startofpacket
		.in0_endofpacket   (trans0_t2h_endofpacket),                 //      .endofpacket
		.in1_data          (capture_pipeline_source0_data),          //   in1.data
		.in1_valid         (capture_pipeline_source0_valid),         //      .valid
		.in1_ready         (capture_pipeline_source0_ready),         //      .ready
		.in1_startofpacket (capture_pipeline_source0_startofpacket), //      .startofpacket
		.in1_endofpacket   (capture_pipeline_source0_endofpacket)    //      .endofpacket
	);

	altera_trace_transacto_lite #(
		.ADDR_WIDTH       (8),
		.DEBUG_PIPE_WIDTH (8),
		.DATA_WIDTH       (32),
		.USE_RDV          (1)
	) trans0 (
		.clk                    (clk_clk),                     //    clk.clk
		.arst_n                 (~debug_reset_0_reset),        //  reset.reset_n
		.dbg_in_ready           (demux_out0_ready),            //    h2t.ready
		.dbg_in_sop             (demux_out0_startofpacket),    //       .startofpacket
		.dbg_in_valid           (demux_out0_valid),            //       .valid
		.dbg_in_eop             (demux_out0_endofpacket),      //       .endofpacket
		.dbg_in_data            (demux_out0_data),             //       .data
		.dbg_out_ready          (trans0_t2h_ready),            //    t2h.ready
		.dbg_out_valid          (trans0_t2h_valid),            //       .valid
		.dbg_out_sop            (trans0_t2h_startofpacket),    //       .startofpacket
		.dbg_out_eop            (trans0_t2h_endofpacket),      //       .endofpacket
		.dbg_out_data           (trans0_t2h_data),             //       .data
		.master_write           (trans0_master_write),         // master.write
		.master_read            (trans0_master_read),          //       .read
		.master_address         (trans0_master_address),       //       .address
		.master_write_data      (trans0_master_writedata),     //       .writedata
		.master_waitrequest     (trans0_master_waitrequest),   //       .waitrequest
		.master_read_data_valid (trans0_master_readdatavalid), //       .readdatavalid
		.master_readdata        (trans0_master_readdata),      //       .readdata
		.enable                 (1'b1)                         // (terminated)
	);

	altera_trace_rom #(
		.NUM_REGS         (5),
		.ADDR_WIDTH       (3),
		.DATA_WIDTH       (32),
		.REG_VALUE_STRING ("000010280000000102FAF0800000000100000001")
	) rom (
		.clk          (clk_clk),                            //   clk.clk
		.rom_read     (mm_interconnect_0_rom_rom_read),     //   rom.read
		.rom_address  (mm_interconnect_0_rom_rom_address),  //      .address
		.rom_readdata (mm_interconnect_0_rom_rom_readdata), //      .readdata
		.arst_n       (~debug_reset_0_reset)                // reset.reset_n
	);

	altera_trace_capture_controller #(
		.DEVICE_FAMILY           ("MAX 10"),
		.TRACE_DATA_WIDTH        (32),
		.TRACE_SYMBOL_WIDTH      (8),
		.TRACE_CHNL_WIDTH        (1),
		.BUFF_ADDR_WIDTH         (13),
		.BUFF_LIMIT_LO           (0),
		.BUFF_SIZE               (8192),
		.PACKET_LEN_BITS         (6),
		.NUM_PPD                 (2),
		.MAX_OUT_PACKET_LENGTH   (1024),
		.ALIGNMENT_BOUNDARIES    (0),
		.CREDIT_WIDTH            (10),
		.WAKE_UP_MODE            ("IDLE"),
		.PERIODIC_TS_REQ_STARTUP (0),
		.DEBUG_READBACK          (1)
	) capture (
		.clk                   (clk_clk),                                       //               clk.clk
		.arst_n                (~debug_reset_0_reset),                          //             reset.reset_n
		.async_ts_sync_clk     (capture_st_sync_req_clk_clk),                   //   st_sync_req_clk.clk
		.trace_packet_ready    (capture_pipe_source0_ready),                    // trace_packet_sink.ready
		.trace_packet_valid    (capture_pipe_source0_valid),                    //                  .valid
		.trace_packet_sop      (capture_pipe_source0_startofpacket),            //                  .startofpacket
		.trace_packet_eop      (capture_pipe_source0_endofpacket),              //                  .endofpacket
		.trace_packet_data     (capture_pipe_source0_data),                     //                  .data
		.trace_packet_chnl     (capture_pipe_source0_channel),                  //                  .channel
		.trace_packet_empty    (capture_pipe_source0_empty),                    //                  .empty
		.dbg_out_ready         (capture_t2h_ready),                             //               t2h.ready
		.dbg_out_valid         (capture_t2h_valid),                             //                  .valid
		.dbg_out_sop           (capture_t2h_startofpacket),                     //                  .startofpacket
		.dbg_out_eop           (capture_t2h_endofpacket),                       //                  .endofpacket
		.dbg_out_data          (capture_t2h_data),                              //                  .data
		.dbg_out_empty         (capture_t2h_empty),                             //                  .empty
		.stg_m_write           (capture_storage_mm_master_write),               // storage_mm_master.write
		.stg_m_read            (capture_storage_mm_master_read),                //                  .read
		.stg_m_address         (capture_storage_mm_master_address),             //                  .address
		.stg_m_write_data      (capture_storage_mm_master_writedata),           //                  .writedata
		.stg_m_waitrequest     (capture_storage_mm_master_waitrequest),         //                  .waitrequest
		.stg_m_read_data_valid (capture_storage_mm_master_readdatavalid),       //                  .readdatavalid
		.stg_m_readdata        (capture_storage_mm_master_readdata),            //                  .readdata
		.csr_s_write           (mm_interconnect_0_capture_csr_slave_write),     //         csr_slave.write
		.csr_s_read            (mm_interconnect_0_capture_csr_slave_read),      //                  .read
		.csr_s_address         (mm_interconnect_0_capture_csr_slave_address),   //                  .address
		.csr_s_write_data      (mm_interconnect_0_capture_csr_slave_writedata), //                  .writedata
		.csr_s_readdata        (mm_interconnect_0_capture_csr_slave_readdata)   //                  .readdata
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (4),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (1),
		.EMPTY_WIDTH      (2),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) wide_capture_pipeline (
		.clk               (clk_clk),                                     //       cr0.clk
		.reset             (debug_reset_0_reset),                         // cr0_reset.reset
		.in_ready          (capture_t2h_ready),                           //     sink0.ready
		.in_valid          (capture_t2h_valid),                           //          .valid
		.in_startofpacket  (capture_t2h_startofpacket),                   //          .startofpacket
		.in_endofpacket    (capture_t2h_endofpacket),                     //          .endofpacket
		.in_empty          (capture_t2h_empty),                           //          .empty
		.in_data           (capture_t2h_data),                            //          .data
		.out_ready         (wide_capture_pipeline_source0_ready),         //   source0.ready
		.out_valid         (wide_capture_pipeline_source0_valid),         //          .valid
		.out_startofpacket (wide_capture_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (wide_capture_pipeline_source0_endofpacket),   //          .endofpacket
		.out_empty         (wide_capture_pipeline_source0_empty),         //          .empty
		.out_data          (wide_capture_pipeline_source0_data),          //          .data
		.out_error         (),                                            // (terminated)
		.in_error          (1'b0),                                        // (terminated)
		.out_channel       (),                                            // (terminated)
		.in_channel        (1'b0)                                         // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_capture_width capture_width (
		.clk               (clk_clk),                                     //   clk.clk
		.reset_n           (~debug_reset_0_reset),                        // reset.reset_n
		.in_data           (wide_capture_pipeline_source0_data),          //    in.data
		.in_valid          (wide_capture_pipeline_source0_valid),         //      .valid
		.in_ready          (wide_capture_pipeline_source0_ready),         //      .ready
		.in_startofpacket  (wide_capture_pipeline_source0_startofpacket), //      .startofpacket
		.in_endofpacket    (wide_capture_pipeline_source0_endofpacket),   //      .endofpacket
		.in_empty          (wide_capture_pipeline_source0_empty),         //      .empty
		.out_data          (capture_width_out_data),                      //   out.data
		.out_valid         (capture_width_out_valid),                     //      .valid
		.out_ready         (capture_width_out_ready),                     //      .ready
		.out_startofpacket (capture_width_out_startofpacket),             //      .startofpacket
		.out_endofpacket   (capture_width_out_endofpacket)                //      .endofpacket
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) capture_pipeline (
		.clk               (clk_clk),                                //       cr0.clk
		.reset             (debug_reset_0_reset),                    // cr0_reset.reset
		.in_ready          (capture_width_out_ready),                //     sink0.ready
		.in_valid          (capture_width_out_valid),                //          .valid
		.in_startofpacket  (capture_width_out_startofpacket),        //          .startofpacket
		.in_endofpacket    (capture_width_out_endofpacket),          //          .endofpacket
		.in_data           (capture_width_out_data),                 //          .data
		.out_ready         (capture_pipeline_source0_ready),         //   source0.ready
		.out_valid         (capture_pipeline_source0_valid),         //          .valid
		.out_startofpacket (capture_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (capture_pipeline_source0_endofpacket),   //          .endofpacket
		.out_data          (capture_pipeline_source0_data),          //          .data
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0),                                   // (terminated)
		.out_channel       (),                                       // (terminated)
		.in_channel        (1'b0)                                    // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_mem mem (
		.clk        (clk_clk),                             //   clk1.clk
		.address    (mm_interconnect_1_mem_s1_address),    //     s1.address
		.clken      (mm_interconnect_1_mem_s1_clken),      //       .clken
		.chipselect (mm_interconnect_1_mem_s1_chipselect), //       .chipselect
		.write      (mm_interconnect_1_mem_s1_write),      //       .write
		.readdata   (mm_interconnect_1_mem_s1_readdata),   //       .readdata
		.writedata  (mm_interconnect_1_mem_s1_writedata),  //       .writedata
		.byteenable (mm_interconnect_1_mem_s1_byteenable), //       .byteenable
		.reset      (debug_reset_0_reset),                 // reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req),  //       .reset_req
		.freeze     (1'b0)                                 // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (4),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (1),
		.EMPTY_WIDTH      (2),
		.CHANNEL_WIDTH    (1),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) capture_pipe (
		.clk               (clk_clk),                            //       cr0.clk
		.reset             (debug_reset_0_reset),                // cr0_reset.reset
		.in_ready          (capture_remap_out_ready),            //     sink0.ready
		.in_valid          (capture_remap_out_valid),            //          .valid
		.in_startofpacket  (capture_remap_out_startofpacket),    //          .startofpacket
		.in_endofpacket    (capture_remap_out_endofpacket),      //          .endofpacket
		.in_empty          (capture_remap_out_empty),            //          .empty
		.in_data           (capture_remap_out_data),             //          .data
		.in_channel        (capture_remap_out_channel),          //          .channel
		.out_ready         (capture_pipe_source0_ready),         //   source0.ready
		.out_valid         (capture_pipe_source0_valid),         //          .valid
		.out_startofpacket (capture_pipe_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (capture_pipe_source0_endofpacket),   //          .endofpacket
		.out_empty         (capture_pipe_source0_empty),         //          .empty
		.out_data          (capture_pipe_source0_data),          //          .data
		.out_channel       (capture_pipe_source0_channel),       //          .channel
		.out_error         (),                                   // (terminated)
		.in_error          (1'b0)                                // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_capture_remap capture_remap (
		.clk               (clk_clk),                         //   clk.clk
		.reset             (debug_reset_0_reset),             // reset.reset
		.in_ready          (capture_mux0_out_ready),          //    in.ready
		.in_valid          (capture_mux0_out_valid),          //      .valid
		.in_data           (capture_mux0_out_data),           //      .data
		.in_startofpacket  (capture_mux0_out_startofpacket),  //      .startofpacket
		.in_endofpacket    (capture_mux0_out_endofpacket),    //      .endofpacket
		.in_channel        (capture_mux0_out_channel),        //      .channel
		.in_empty          (capture_mux0_out_empty),          //      .empty
		.out_ready         (capture_remap_out_ready),         //   out.ready
		.out_valid         (capture_remap_out_valid),         //      .valid
		.out_data          (capture_remap_out_data),          //      .data
		.out_startofpacket (capture_remap_out_startofpacket), //      .startofpacket
		.out_endofpacket   (capture_remap_out_endofpacket),   //      .endofpacket
		.out_channel       (capture_remap_out_channel),       //      .channel
		.out_empty         (capture_remap_out_empty)          //      .empty
	);

	alt_sld_fab_alt_sld_fab_trfabric_capture_mux0 capture_mux0 (
		.clk               (clk_clk),                               //   clk.clk
		.reset_n           (~debug_reset_0_reset),                  // reset.reset_n
		.out_data          (capture_mux0_out_data),                 //   out.data
		.out_valid         (capture_mux0_out_valid),                //      .valid
		.out_ready         (capture_mux0_out_ready),                //      .ready
		.out_startofpacket (capture_mux0_out_startofpacket),        //      .startofpacket
		.out_endofpacket   (capture_mux0_out_endofpacket),          //      .endofpacket
		.out_empty         (capture_mux0_out_empty),                //      .empty
		.out_channel       (capture_mux0_out_channel),              //      .channel
		.in0_data          (sync_pipe0_source0_data),               //   in0.data
		.in0_valid         (sync_pipe0_source0_valid),              //      .valid
		.in0_ready         (sync_pipe0_source0_ready),              //      .ready
		.in0_startofpacket (sync_pipe0_source0_startofpacket),      //      .startofpacket
		.in0_endofpacket   (sync_pipe0_source0_endofpacket),        //      .endofpacket
		.in0_empty         (sync_pipe0_source0_empty),              //      .empty
		.in1_data          (capture_pipe0_1_source0_data),          //   in1.data
		.in1_valid         (capture_pipe0_1_source0_valid),         //      .valid
		.in1_ready         (capture_pipe0_1_source0_ready),         //      .ready
		.in1_startofpacket (capture_pipe0_1_source0_startofpacket), //      .startofpacket
		.in1_endofpacket   (capture_pipe0_1_source0_endofpacket),   //      .endofpacket
		.in1_empty         (capture_pipe0_1_source0_empty)          //      .empty
	);

	altera_trace_timestamp_monitor #(
		.TRACE_DATA_WIDTH   (32),
		.TRACE_SYMBOL_WIDTH (8),
		.FULL_TS_LENGTH     (40),
		.SHORT_TS_BITS      (16),
		.SYNC_DEPTH         (3)
	) sync0 (
		.clk               (clk_clk),                     //       clock.clk
		.arst_n            (~debug_reset_0_reset),        //  reset_sink.reset_n
		.async_ts_sync_clk (capture_st_sync_req_clk_clk), // ts_sync_req.clk
		.av_st_tr_ready    (sync0_capture_ready),         //     capture.ready
		.av_st_tr_valid    (sync0_capture_valid),         //            .valid
		.av_st_tr_sop      (sync0_capture_startofpacket), //            .startofpacket
		.av_st_tr_eop      (sync0_capture_endofpacket),   //            .endofpacket
		.av_st_tr_data     (sync0_capture_data),          //            .data
		.av_st_tr_empty    (sync0_capture_empty),         //            .empty
		.full_ts           ()                             // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (4),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (1),
		.EMPTY_WIDTH      (2),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) sync_pipe0 (
		.clk               (clk_clk),                          //       cr0.clk
		.reset             (debug_reset_0_reset),              // cr0_reset.reset
		.in_ready          (sync0_capture_ready),              //     sink0.ready
		.in_valid          (sync0_capture_valid),              //          .valid
		.in_startofpacket  (sync0_capture_startofpacket),      //          .startofpacket
		.in_endofpacket    (sync0_capture_endofpacket),        //          .endofpacket
		.in_empty          (sync0_capture_empty),              //          .empty
		.in_data           (sync0_capture_data),               //          .data
		.out_ready         (sync_pipe0_source0_ready),         //   source0.ready
		.out_valid         (sync_pipe0_source0_valid),         //          .valid
		.out_startofpacket (sync_pipe0_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (sync_pipe0_source0_endofpacket),   //          .endofpacket
		.out_empty         (sync_pipe0_source0_empty),         //          .empty
		.out_data          (sync_pipe0_source0_data),          //          .data
		.out_error         (),                                 // (terminated)
		.in_error          (1'b0),                             // (terminated)
		.out_channel       (),                                 // (terminated)
		.in_channel        (1'b0)                              // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (4),
		.BITS_PER_SYMBOL  (8),
		.USE_PACKETS      (1),
		.USE_EMPTY        (1),
		.EMPTY_WIDTH      (2),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) capture_pipe0_1 (
		.clk               (clk_clk),                               //       cr0.clk
		.reset             (debug_reset_0_reset),                   // cr0_reset.reset
		.in_ready          (avalon_st_adapter_out_0_ready),         //     sink0.ready
		.in_valid          (avalon_st_adapter_out_0_valid),         //          .valid
		.in_startofpacket  (avalon_st_adapter_out_0_startofpacket), //          .startofpacket
		.in_endofpacket    (avalon_st_adapter_out_0_endofpacket),   //          .endofpacket
		.in_empty          (avalon_st_adapter_out_0_empty),         //          .empty
		.in_data           (avalon_st_adapter_out_0_data),          //          .data
		.out_ready         (capture_pipe0_1_source0_ready),         //   source0.ready
		.out_valid         (capture_pipe0_1_source0_valid),         //          .valid
		.out_startofpacket (capture_pipe0_1_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (capture_pipe0_1_source0_endofpacket),   //          .endofpacket
		.out_empty         (capture_pipe0_1_source0_empty),         //          .empty
		.out_data          (capture_pipe0_1_source0_data),          //          .data
		.out_error         (),                                      // (terminated)
		.in_error          (1'b0),                                  // (terminated)
		.out_channel       (),                                      // (terminated)
		.in_channel        (1'b0)                                   // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (7),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (0),
		.PIPELINE_RESPONSE (0)
	) bridge_0 (
		.clk              (clk_clk),                                     //   clk.clk
		.reset            (debug_reset_0_reset),                         // reset.reset
		.s0_waitrequest   (mm_interconnect_0_bridge_0_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_bridge_0_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_0_bridge_0_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_bridge_0_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_0_bridge_0_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_0_bridge_0_s0_address),       //      .address
		.s0_write         (mm_interconnect_0_bridge_0_s0_write),         //      .write
		.s0_read          (mm_interconnect_0_bridge_0_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_0_bridge_0_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_0_bridge_0_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (bridge_0_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (bridge_0_m0_readdata),                        //      .readdata
		.m0_readdatavalid (bridge_0_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (bridge_0_m0_burstcount),                      //      .burstcount
		.m0_writedata     (bridge_0_m0_writedata),                       //      .writedata
		.m0_address       (bridge_0_m0_address),                         //      .address
		.m0_write         (bridge_0_m0_write),                           //      .write
		.m0_read          (bridge_0_m0_read),                            //      .read
		.m0_byteenable    (bridge_0_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (bridge_0_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                            // (terminated)
		.m0_response      (2'b00)                                        // (terminated)
	);

	alt_sld_fab_alt_sld_fab_trfabric_mm_interconnect_0 mm_interconnect_0 (
		.clock0_out_clk_clk                       (clk_clk),                                       //                     clock0_out_clk.clk
		.trans0_reset_reset_bridge_in_reset_reset (debug_reset_0_reset),                           // trans0_reset_reset_bridge_in_reset.reset
		.trans0_master_address                    (trans0_master_address),                         //                      trans0_master.address
		.trans0_master_waitrequest                (trans0_master_waitrequest),                     //                                   .waitrequest
		.trans0_master_read                       (trans0_master_read),                            //                                   .read
		.trans0_master_readdata                   (trans0_master_readdata),                        //                                   .readdata
		.trans0_master_readdatavalid              (trans0_master_readdatavalid),                   //                                   .readdatavalid
		.trans0_master_write                      (trans0_master_write),                           //                                   .write
		.trans0_master_writedata                  (trans0_master_writedata),                       //                                   .writedata
		.bridge_0_s0_address                      (mm_interconnect_0_bridge_0_s0_address),         //                        bridge_0_s0.address
		.bridge_0_s0_write                        (mm_interconnect_0_bridge_0_s0_write),           //                                   .write
		.bridge_0_s0_read                         (mm_interconnect_0_bridge_0_s0_read),            //                                   .read
		.bridge_0_s0_readdata                     (mm_interconnect_0_bridge_0_s0_readdata),        //                                   .readdata
		.bridge_0_s0_writedata                    (mm_interconnect_0_bridge_0_s0_writedata),       //                                   .writedata
		.bridge_0_s0_burstcount                   (mm_interconnect_0_bridge_0_s0_burstcount),      //                                   .burstcount
		.bridge_0_s0_byteenable                   (mm_interconnect_0_bridge_0_s0_byteenable),      //                                   .byteenable
		.bridge_0_s0_readdatavalid                (mm_interconnect_0_bridge_0_s0_readdatavalid),   //                                   .readdatavalid
		.bridge_0_s0_waitrequest                  (mm_interconnect_0_bridge_0_s0_waitrequest),     //                                   .waitrequest
		.bridge_0_s0_debugaccess                  (mm_interconnect_0_bridge_0_s0_debugaccess),     //                                   .debugaccess
		.capture_csr_slave_address                (mm_interconnect_0_capture_csr_slave_address),   //                  capture_csr_slave.address
		.capture_csr_slave_write                  (mm_interconnect_0_capture_csr_slave_write),     //                                   .write
		.capture_csr_slave_read                   (mm_interconnect_0_capture_csr_slave_read),      //                                   .read
		.capture_csr_slave_readdata               (mm_interconnect_0_capture_csr_slave_readdata),  //                                   .readdata
		.capture_csr_slave_writedata              (mm_interconnect_0_capture_csr_slave_writedata), //                                   .writedata
		.rom_rom_address                          (mm_interconnect_0_rom_rom_address),             //                            rom_rom.address
		.rom_rom_read                             (mm_interconnect_0_rom_rom_read),                //                                   .read
		.rom_rom_readdata                         (mm_interconnect_0_rom_rom_readdata)             //                                   .readdata
	);

	alt_sld_fab_alt_sld_fab_trfabric_mm_interconnect_1 mm_interconnect_1 (
		.clock0_out_clk_clk                        (clk_clk),                                 //                      clock0_out_clk.clk
		.capture_reset_reset_bridge_in_reset_reset (debug_reset_0_reset),                     // capture_reset_reset_bridge_in_reset.reset
		.capture_storage_mm_master_address         (capture_storage_mm_master_address),       //           capture_storage_mm_master.address
		.capture_storage_mm_master_waitrequest     (capture_storage_mm_master_waitrequest),   //                                    .waitrequest
		.capture_storage_mm_master_read            (capture_storage_mm_master_read),          //                                    .read
		.capture_storage_mm_master_readdata        (capture_storage_mm_master_readdata),      //                                    .readdata
		.capture_storage_mm_master_readdatavalid   (capture_storage_mm_master_readdatavalid), //                                    .readdatavalid
		.capture_storage_mm_master_write           (capture_storage_mm_master_write),         //                                    .write
		.capture_storage_mm_master_writedata       (capture_storage_mm_master_writedata),     //                                    .writedata
		.mem_s1_address                            (mm_interconnect_1_mem_s1_address),        //                              mem_s1.address
		.mem_s1_write                              (mm_interconnect_1_mem_s1_write),          //                                    .write
		.mem_s1_readdata                           (mm_interconnect_1_mem_s1_readdata),       //                                    .readdata
		.mem_s1_writedata                          (mm_interconnect_1_mem_s1_writedata),      //                                    .writedata
		.mem_s1_byteenable                         (mm_interconnect_1_mem_s1_byteenable),     //                                    .byteenable
		.mem_s1_chipselect                         (mm_interconnect_1_mem_s1_chipselect),     //                                    .chipselect
		.mem_s1_clken                              (mm_interconnect_1_mem_s1_clken)           //                                    .clken
	);

	alt_sld_fab_alt_sld_fab_trfabric_mm_interconnect_2 mm_interconnect_2 (
		.clock0_out_clk_clk                         (clk_clk),                   //                       clock0_out_clk.clk
		.bridge_0_reset_reset_bridge_in_reset_reset (debug_reset_0_reset),       // bridge_0_reset_reset_bridge_in_reset.reset
		.bridge_0_m0_address                        (bridge_0_m0_address),       //                          bridge_0_m0.address
		.bridge_0_m0_waitrequest                    (bridge_0_m0_waitrequest),   //                                     .waitrequest
		.bridge_0_m0_burstcount                     (bridge_0_m0_burstcount),    //                                     .burstcount
		.bridge_0_m0_byteenable                     (bridge_0_m0_byteenable),    //                                     .byteenable
		.bridge_0_m0_read                           (bridge_0_m0_read),          //                                     .read
		.bridge_0_m0_readdata                       (bridge_0_m0_readdata),      //                                     .readdata
		.bridge_0_m0_readdatavalid                  (bridge_0_m0_readdatavalid), //                                     .readdatavalid
		.bridge_0_m0_write                          (bridge_0_m0_write),         //                                     .write
		.bridge_0_m0_writedata                      (bridge_0_m0_writedata),     //                                     .writedata
		.bridge_0_m0_debugaccess                    (bridge_0_m0_debugaccess),   //                                     .debugaccess
		.tbridge_0_int_control_address              (control_0_address),         //                tbridge_0_int_control.address
		.tbridge_0_int_control_write                (control_0_write),           //                                     .write
		.tbridge_0_int_control_read                 (control_0_read),            //                                     .read
		.tbridge_0_int_control_readdata             (control_0_readdata),        //                                     .readdata
		.tbridge_0_int_control_writedata            (control_0_writedata)        //                                     .writedata
	);

	alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter #(
		.inBitsPerSymbol (8),
		.inUsePackets    (1),
		.inDataWidth     (8),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (32),
		.outChannelWidth (0),
		.outErrorWidth   (0),
		.outUseEmptyPort (1),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk        (clk_clk),                               // in_clk_0.clk
		.in_rst_0_reset      (debug_reset_0_reset),                   // in_rst_0.reset
		.in_0_data           (capture_0_data),                        //     in_0.data
		.in_0_valid          (capture_0_valid),                       //         .valid
		.in_0_ready          (capture_0_ready),                       //         .ready
		.in_0_startofpacket  (capture_0_startofpacket),               //         .startofpacket
		.in_0_endofpacket    (capture_0_endofpacket),                 //         .endofpacket
		.out_0_data          (avalon_st_adapter_out_0_data),          //    out_0.data
		.out_0_valid         (avalon_st_adapter_out_0_valid),         //         .valid
		.out_0_ready         (avalon_st_adapter_out_0_ready),         //         .ready
		.out_0_startofpacket (avalon_st_adapter_out_0_startofpacket), //         .startofpacket
		.out_0_endofpacket   (avalon_st_adapter_out_0_endofpacket),   //         .endofpacket
		.out_0_empty         (avalon_st_adapter_out_0_empty)          //         .empty
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset_reset),                        // reset_in0.reset
		.clk            (clk_clk),                            //       clk.clk
		.reset_out      (debug_reset_0_reset),                // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_in1      (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

	assign debug_reset_reset = debug_reset_0_reset;

endmodule
