AKohl3
New Contributor
New ContributorHi, Have been able to add the qsys ADC module to the project but on final compilation the flow summary reports 0/1 ADC blocks in use even after I have selected all ports ANA1IN1 to ADC1IN8 in the qsys window.
From what i can tell the ADC module only needs a command to select which port to sample so how do i make pin assignments to confirm the ADC in use!
Hello there ,
Here attached the screen shot and the modfied design file with ADC block utilization mentioned in the compliation report.
As of understood from the design you provided , quartus is optimizing the ADC block since it is no where used in the design.
In the modified design i instantiated the ADC input and clock as Input port which restrict the quartus to optimize the same.
Hope helps ,
Thank you ,
Regards,
Sree
