Good design, bad design - one-clock-states in state-machines

Question

Hi,  another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition.  example:  
if (rising_edge(clock)) then
   case (current_state) is
   --------------------------------------------------------------------
   -- Idle State
   --------------------------------------------------------------------
   when S000 =&gt;
      
      Signal_Data   &lt;= X"00";
      Signal_Ctrl     &lt;='0';                   
                        
      sig_Start_IN            &lt;= Start_IN;
                        
      if ((sig_Start_IN = '0') AND (Start_IN = '1')) then
         current_state             &lt;= S010;  
      else
         current_state             &lt;= current_state; 
      end if;
                                                                    
   --------------------------------------------------------------------
   -- State010
   --------------------------------------------------------------------
   when S010 =&gt;       
      
      Signal_Data   &lt;= X"34";
      Signal_Ctrl     &lt;='0';
                        
      current_state &lt;= S020;
                                                                    
   --------------------------------------------------------------------
   -- State020
   --------------------------------------------------------------------
   when S020 =&gt;                            
      
      Signal_Data   &lt;= X"F2";
      Signal_Ctrl     &lt;='1';
                        
      current_state &lt;= S000;
                    
   --------------------------------------------------------------------
   -- What else could be done?
   --------------------------------------------------------------------
   when others =&gt;                                                  
      current_state     &lt;= S000;
   end case;
end if;
  Is this a problem for synthesis?  I never seen such a one-clock-state without condition in other codes before and therefore I don't know is it good or bad to do this. No one ever mentioned such states. What do you think? Save or unsave to do this?  PS: I don't want a discussion about how much sense it makes to implement this or what it can be good for. I just want to know if this will work securely.

altera_forum · Answer

you can do that, no problem. I have state machines many times like that to just cause one clock latency.

altera_forum · Answer

--------------------------------------------------------------------
   -- State010
   --------------------------------------------------------------------
   when S010 =&gt;             
      Signal_Data   &lt;= X"34";
      Signal_Ctrl     &lt;='0';     
      current_state &lt;= waitForMe ;             
   --------------------------------------------------------------------
   -- waitForMe
   --------------------------------------------------------------------
   when waitForMe =&gt;
      Signal_Data   &lt;= X"34";
      Signal_Ctrl     &lt;='0';    
      current_state &lt;= S020;
                                                                    
   --------------------------------------------------------------------
   -- State020
   --------------------------------------------------------------------  now it's safe.

altera_forum · Answer

Often called wait states, for example using a state machine to read from a ram that has a few clocks of latency.

altera_forum · Answer

OK, thank you. So they are safe to use and the synthesis should understand them. Nice.  Ähmm, linas, what are you trying to tell me?????

altera_forum · Answer

As long as you stick to the templates, theres not a lot that is "unsafe" to use.

Aslong as you have:

if rising_edge(clk) then

as the first thing in the process, you can do pretty much anything inside it.

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Good design, bad design -> one-clock-states in state-machines

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