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Altera_Forum's avatar
Altera_Forum
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10 years ago

Good design, bad design -> one-clock-states in state-machines

Hi,

another question is giong through my mind:

Is it possible (good design) to create one or more states which exit to next state without any condition.

example: 


if (rising_edge(clock)) then
   case (current_state) is
   --------------------------------------------------------------------
   -- Idle State
   --------------------------------------------------------------------
   when S000 =>
      
      Signal_Data   <= X"00";
      Signal_Ctrl     <='0';                   
                        
      sig_Start_IN            <= Start_IN;
                        
      if ((sig_Start_IN = '0') AND (Start_IN = '1')) then
         current_state             <= S010;  
      else
         current_state             <= current_state; 
      end if;
                                                                    
   --------------------------------------------------------------------
   -- State010
   --------------------------------------------------------------------
   when S010 =>       
      
      Signal_Data   <= X"34";
      Signal_Ctrl     <='0';
                        
      current_state <= S020;
                                                                    
   --------------------------------------------------------------------
   -- State020
   --------------------------------------------------------------------
   when S020 =>                            
      
      Signal_Data   <= X"F2";
      Signal_Ctrl     <='1';
                        
      current_state <= S000;
                    
   --------------------------------------------------------------------
   -- What else could be done?
   --------------------------------------------------------------------
   when others =>                                                  
      current_state     <= S000;
   end case;
end if;

Is this a problem for synthesis?

I never seen such a one-clock-state without condition in other codes before and therefore I don't know is it good or bad to do this. No one ever mentioned such states.

What do you think? Save or unsave to do this?

PS: I don't want a discussion about how much sense it makes to implement this or what it can be good for. I just want to know if this will work securely.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    you can do that, no problem. I have state machines many times like that to just cause one clock latency.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --------------------------------------------------------------------
   -- State010
   --------------------------------------------------------------------
   when S010 =>             
      Signal_Data   <= X"34";
      Signal_Ctrl     <='0';     
      current_state <= waitForMe ;             
   --------------------------------------------------------------------
   -- waitForMe
   --------------------------------------------------------------------
   when waitForMe =>
      Signal_Data   <= X"34";
      Signal_Ctrl     <='0';    
      current_state <= S020;
                                                                    
   --------------------------------------------------------------------
   -- State020
   --------------------------------------------------------------------

    now it's safe.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Often called wait states, for example using a state machine to read from a ram that has a few clocks of latency.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    OK, thank you. So they are safe to use and the synthesis should understand them. Nice.

    Ähmm, linas, what are you trying to tell me?????
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    As long as you stick to the templates, theres not a lot that is "unsafe" to use.

    Aslong as you have:

    if rising_edge(clk) then

    as the first thing in the process, you can do pretty much anything inside it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I added a wait state in your code. Nothing important happens there, just a delay of one clock cycle. One still needs to define control signals (Signal_Data and Signal_Ctr for this case) in this state, otherwise latches will be generated.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    @linas: Ah, now I know. Thank you.

    @tricky: Yes, this was an easy to learn lesson. Above all for me, I don't have to care about the sensitivity-list anymore ;)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    @linas: Ah, now I know. Thank you.

    @tricky: Yes, this was an easy to learn lesson. Above all for me, I don't have to care about the sensitivity-list anymore ;)

    --- Quote End ---

    If you are bothered by having to list all the input signals in a VHDL sensitivity list, you no longer have to do so. VHDL-2008 has a construct that automatically includes all inputs to a process, thus simplifying the sensitivity list. For example:

    //Old way

    my_old_process: process (A,B,my_reset, my_input)

    begin.....

    //New way. Just use the keyword "all"

    my_better_process: process(all)

    begin....

    Robert

    lead trainer VHDL and Verilog

    www.digitaldesignconcepts.org