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Altera_Forum
Honored Contributor
Honored ContributorGood design, bad design -> one-clock-states in state-machines
Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example:
if (rising_edge(...
Altera_ForumHonored Contributor
Honored ContributorI added a wait state in your code. Nothing important happens there, just a delay of one clock cycle. One still needs to define control signals (Signal_Data and Signal_Ctr for this case) in this state, otherwise latches will be generated.
