Forum Discussion
Altera_Forum
Honored Contributor
11 years agoGood design, bad design -> one-clock-states in state-machines
Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example:
if (rising_edge(...
Altera_Forum
Honored Contributor
11 years ago@linas: Ah, now I know. Thank you.
@tricky: Yes, this was an easy to learn lesson. Above all for me, I don't have to care about the sensitivity-list anymore ;)