Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Good design, bad design -> one-clock-states in state-machines

Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example: if (rising_edge(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Often called wait states, for example using a state machine to read from a ram that has a few clocks of latency.