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Altera_Forum's avatar
Altera_Forum
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10 years ago

Good design, bad design -> one-clock-states in state-machines

Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example: if (rising_edge(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--------------------------------------------------------------------
   -- State010
   --------------------------------------------------------------------
   when S010 =>             
      Signal_Data   <= X"34";
      Signal_Ctrl     <='0';     
      current_state <= waitForMe ;             
   --------------------------------------------------------------------
   -- waitForMe
   --------------------------------------------------------------------
   when waitForMe =>
      Signal_Data   <= X"34";
      Signal_Ctrl     <='0';    
      current_state <= S020;
                                                                    
   --------------------------------------------------------------------
   -- State020
   --------------------------------------------------------------------

now it's safe.