Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorGood design, bad design -> one-clock-states in state-machines
Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example:
if (rising_edge(...
Altera_ForumHonored Contributor
Honored ContributorOK, thank you. So they are safe to use and the synthesis should understand them. Nice.
Ähmm, linas, what are you trying to tell me?????
