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Altera_Forum
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10 years ago

Good design, bad design -> one-clock-states in state-machines

Hi, another question is giong through my mind: Is it possible (good design) to create one or more states which exit to next state without any condition. example: if (rising_edge(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

OK, thank you. So they are safe to use and the synthesis should understand them. Nice.

Ähmm, linas, what are you trying to tell me?????