FIR, Dual clock FIFO and FIR integration synthesize doubts...

any one has any clue..?? or need more information???

really need help... thank you =)

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I can't follow your assumption, that there should be a difference between both variants, if you use a FIFO. A 100 MHz data sink can possibly connect to a 50 MHz data source without a FIFO, if the clocks are supplied from a PLL with suitable phase. But with a FIFO, only maximum speed has to be kept.

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Hi, thanks a lot for the reply.

Because I used SOPC builder to connect these two FIRs. The Dual-Clock FIFO is a must as the Avalon ST interface can only be used when the two ports (source data and sink data) have the same clock domains.

I suppose the Avalon ST interface will be different for different combination of clocks? Or is it? e.g. for 51Mhz is interfaced to 50Mhz, it is supposed to be more complicated to avoid the data loss? Or my understanding is completely wrong?

By the way, I didn't use PLL, the clock is external clock.

Thanks!

If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case.

However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.

So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.

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If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case.

However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.

So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.

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Hi, thanks a lot for the explanation. Then there must be situations when the FIFO cannot guarantee no data loss, right? Do you have any idea what are those cases? I can't really find much useful information from the DC FIFO user guide downloaded from altera website..

thank you

No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO).

There are stochastic conditions that can cause metastability.

You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.

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No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO).

There are stochastic conditions that can cause metastability.

You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.

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Hi, do you know where I can find some more details about the Dual Clock FIFO? Like how it works, the internal connection, the specification and so forth?

The altera document is too abstract and information limited..

Thank you so much!

This is the only documentation I know of

http://www.altera.com/literature/hb/nios2/qts_qii55014.pdf

http://www.altera.com/literature/ug/ug_fifo.pdf