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Altera_Forum
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16 years ago

FIR, Dual clock FIFO and FIR integration synthesize doubts...

Hi, everyone, I am using Quartus II 9.0 sp2. I am connecting two FIRs together, between which I have put a Dual-Clock FIFO because those two FIRs are operating in different clock domains. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO).

There are stochastic conditions that can cause metastability.

You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.