FIR, Dual clock FIFO and FIR integration synthesize doubts...

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No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO).

There are stochastic conditions that can cause metastability.

You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.

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Hi, do you know where I can find some more details about the Dual Clock FIFO? Like how it works, the internal connection, the specification and so forth?

The altera document is too abstract and information limited..

Thank you so much!