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If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case.
However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.
So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.
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Hi, thanks a lot for the explanation. Then there must be situations when the FIFO cannot guarantee no data loss, right? Do you have any idea what are those cases? I can't really find much useful information from the DC FIFO user guide downloaded from altera website..
thank you
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