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I can't follow your assumption, that there should be a difference between both variants, if you use a FIFO. A 100 MHz data sink can possibly connect to a 50 MHz data source without a FIFO, if the clocks are supplied from a PLL with suitable phase. But with a FIFO, only maximum speed has to be kept.
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Hi, thanks a lot for the reply.
Because I used SOPC builder to connect these two FIRs. The Dual-Clock FIFO is a must as the Avalon ST interface can only be used when the two ports (source data and sink data) have the same clock domains.
I suppose the Avalon ST interface will be different for different combination of clocks? Or is it? e.g. for 51Mhz is interfaced to 50Mhz, it is supposed to be more complicated to avoid the data loss? Or my understanding is completely wrong?
By the way, I didn't use PLL, the clock is external clock.
Thanks!
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