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Altera_Forum
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16 years ago

FIR, Dual clock FIFO and FIR integration synthesize doubts...

Hi, everyone, I am using Quartus II 9.0 sp2. I am connecting two FIRs together, between which I have put a Dual-Clock FIFO because those two FIRs are operating in different clock domains. ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I can't follow your assumption, that there should be a difference between both variants, if you use a FIFO. A 100 MHz data sink can possibly connect to a 50 MHz data source without a FIFO, if the clocks are supplied from a PLL with suitable phase. But with a FIFO, only maximum speed has to be kept.