FIR, Dual clock FIFO and FIR integration synthesize doubts...

If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case.

However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.

So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.