Forum Discussion
Honored ContributorFIFO Outputs all HiZ in RTL Simulation
Hi All,
I am still a beginner to FPGAs, but I think I'm making good progress. I am able to simulate my own Verilog code in ModelSim-Altera and everything looks correct. However, when I try to simulate an Altera Megafunction (DCFIFO in this case) all of the outputs are always HiZ no matter what inputs I give. I have done a lot of searching but I haven't come across anything which solved my problem. All of the other threads I found usually conclude with "Add the libraries", but I have done that. The code compiles fine. I'm running the simulation with "vsim work.sync_fifo -L altera_mf" Output screenshot is attached. After looking into the generated code it seems like the Megawizard just generates wrappers. How do I get the actual internals to simulate? I also understand the during synthesis a lot of optimization happens. Outputs which are not depended on by the rest of the design get removed. But if I am simulating the module directly, this should not happen, correct? Thanks20 Replies
Altera_ForumFrom the attached waveform, it seems you have tied the FIFO reset signal to one. I think its reset signal is active-high; If so, drive it with '1', and after a few clock cycles drive it with '0'.
More over, issue some write request signals, so that something would be written into it.- Altera_Forum
What did you put in the testbench? It looks like there is nothing more than a clock and a reset stuck at 1
- Altera_Forum
Right now the test bench IS just a clock signal. I added in a reset to 1 in that screenshot just to try it out. Whether it is 1 or 0, the outputs are still HiZ. I also tried what msj suggested, which was drive reset to 1 for a few clocks, then drive to 0. Still no change.
I have also tried some write signals previously. Here's another screenshot. I think this should write 5 bytes of 8'b10101010 to the FIFO. Is this wrong? - Altera_Forum
have you actually connected the clock to the FIFO? how about the other signals?
Post the testbench code? - Altera_Forum
what is clock frequency? Are you simulating a post-place & route design or a pre-synthesis one?
you'd better post your code. - Altera_Forum
I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output.
`timescale 1ns / 100ps module sync_fifo_tb (); // // Inputs to module reg clk; reg wrreq; reg rdreq; reg data; reg sclr; // // Outputs from module wire q; wire usedw; wire full; wire empty; // // Instantiate device sync_fifo U1( .clock(clk), .data(data), .rdreq(rdreq), .sclr(sclr), .wrreq(wrreq), .empty(empty), .full(full), .q(q), .usedw(usedw) ); // // Clock setup always # 5 clk = ~clk; // // Initial setup initial begin clk = 0; sclr = 1; wrreq = 0; rdreq = 0; data = 8'b10101010; # 50 sclr = 0; # 20 wrreq = 1; @(posedge clk); // Wait 5 clocks @(posedge clk); @(posedge clk); @(posedge clk); @(posedge clk); # 5 wrreq = 0; end endmodule - Altera_Forum
I posted a test bench file, but that is awaiting moderation for some reason. In the meantime, I'm not entirely sure how to answer that question msj.
I am opening the Verilog files in a ModelSim project and compiling them there. I am then running the vsim command on the module itself. The module was generated using the Quartus II Megawizard. There is no code of my own, except for the test bench. I don't think this is a problem with code though. This problem is occurring for any of the generated megafunctions. Even when I try to simulate a PLL megafunction, which takes no inputs but a 50MHz clock, has HiZ outputs. I must be doing something else wrong, but I have no idea what it might be. - Altera_Forum
meanwhile, run simulator without optimization:
vsim -novopt work.sync_... - Altera_Forum
"vsim -novopt work.sync_fifo_tb -L altera_mf" produces no change. I even recompiled with -O0 first.
- Altera_Forum--- Quote Start --- I'll be totally honest with you, I was running commands directly in ModelSim just to experiement. That is probably a dumb thing to do. I wrote a test bench which produces the attached output. --- Quote End --- Ive unblocked all your posts - posting code with low post numbers requires moderation. No, that is a perfectly normal thing to do (and much better than running it from quartus). Have you compiled the sync_fifo block? where is the code for that?
