FGPA Reset Issue

@Vicky​

our quartus version is 13.1 web edition

DE0-NANO board with EP4CE22F17C6 FPGA.

Our design consist of a I2S state machine, 32 up sample filter, 8 up sample filter, and a sigma delta modulator. we generate all the vhdl files using simulink hdl coder and combine them in quartus. Our output rate is 11 MHz, our reset circuit gets an clock signal of 11 MHz.

here is the screen shot of the bdf file.

@KennyT_Intel​

no these are not measured constrains. this is just a simple sdc file. we still dont have our final hardware. we dont have any timing violation so far. could you help us update our SDC file, in case that helps.

Hi,

Please, provide the below details for replication,

1. Quartus edition & version.
2. Board/Kit used
3. Screenshot of bdf design.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Looking into how you write the constrain, did you make sure that the value 0.5 is the right value get from the board? Did you check you have timing violation?

Also, did you run a simulation test in Modelsim to make sure that the functional is correct?​

Hi,

Can you please debug the small circuits with Modelsim using testbench ,

1. Only for first two Flipflop circuit
2. Including FPGA inst. circuit
3. Including last four Flipflop circuit

Refer the below handbook for SDC,

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51006.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

@Vicky​

thanks for your suggestion. we didn't manage to run the test bench with model sim due to lack of experience. Maybe giving a bit more insight to the project helps to get few more suggestions

our system consist of a I2S interface + Up sampling Filter + Sigma Delta Modulator. Our input signal is 44.1 kHz and output is 11.2 Mhz DSD signal. our master clock to the FPGA is 50 MHz. Now we try to synchronize the reset with two flip flops as shown in the above BLDC diagram with the master clock as input to the flip flops. But what happens is the reset does not work every time, on the scope we can see data, but no output. This is a project for a customer, would it be possible to send you the archived project via mail internally, so you could have a look. just to avoid the parts of the design file going public

Hi,

Please refer the below links for NativeLink simulation.

1. https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/simulation/modelsim/exm-ncsim-native-link.html
2. https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/simulation/modelsim/simulation-nativelink-howto.html
3. https://www.youtube.com/watch?v=PmVVXQchv2c

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)