FGPA Reset Issue

@Vicky​

our quartus version is 13.1 web edition

DE0-NANO board with EP4CE22F17C6 FPGA.

Our design consist of a I2S state machine, 32 up sample filter, 8 up sample filter, and a sigma delta modulator. we generate all the vhdl files using simulink hdl coder and combine them in quartus. Our output rate is 11 MHz, our reset circuit gets an clock signal of 11 MHz.

here is the screen shot of the bdf file.

@KennyT_Intel​

no these are not measured constrains. this is just a simple sdc file. we still dont have our final hardware. we dont have any timing violation so far. could you help us update our SDC file, in case that helps.