New Contributor
New Contributorthanks for your suggestion. we didn't manage to run the test bench with model sim due to lack of experience. Maybe giving a bit more insight to the project helps to get few more suggestions
our system consist of a I2S interface + Up sampling Filter + Sigma Delta Modulator. Our input signal is 44.1 kHz and output is 11.2 Mhz DSD signal. our master clock to the FPGA is 50 MHz. Now we try to synchronize the reset with two flip flops as shown in the above BLDC diagram with the master clock as input to the flip flops. But what happens is the reset does not work every time, on the scope we can see data, but no output. This is a project for a customer, would it be possible to send you the archived project via mail internally, so you could have a look. just to avoid the parts of the design file going public
