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Altera_Forum
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13 years ago

Errors or Warnings when using EPCS controller in hierarchical design

I have a hierarchical design with an EPCS controller instantiated in the bottom level. I am using a Cyclone IV with a 256 pin FPGA (EP4CE15F17).

In the EPCS controller there is a Conduit Endpoint named “external”. If I don’t export that Endpoint I get the following warning from Qsys “Warning: System.epcs_flash_controller_0: epcs_flash_controller_0.external must be exported, or connected to a matching conduit.”

If I ignore that warning and build the design then it compiles successfully. However I can’t confirm that the configuration flash signals went to the dedicated pins in Pin Planner. If I look at all of the assignable pins in Pin Planner it doesn’t list anything connected to pin H1, which should be the DCLK signal on my package. The same is true for ASD0, Data0 and CS0.

If I export the EPCS Endpoint at the lowest level then I don’t get any Qsys warnings or errors. However during fitting Quartus is mapping the exported EPCS signals to pins other than the dedicated pins. In Pin Planner this is what I see:

subsytem_0_epcs_flash_controller_0_external_data0 Input PIN_P8

subsytem_0_epcs_flash_controller_0_external_dclk Output PIN_L9

subsytem_0_epcs_flash_controller_0_external_sce Output PIN_D8

subsytem_0_epcs_flash_controller_0_external_sdo Output PIN_E9

If I explicitly connect the EPCS outputs to the correct device pins, when I compile the design I get errors like this for all four EPCS signals.

“Error (176310): Can't place multiple pins assigned to pin location Pin_H1 (IOPAD_X0_Y20_N14)

Info (176311): Pin subsytem_0_epcs_flash_controller_0_external_dclk is assigned to pin location Pin_H1 (IOPAD_X0_Y20_N14)

Info (176311): Pin ~ALTERA_DCLK~ is assigned to pin location Pin_H1 (IOPAD_X0_Y20_N14)”

So I’m in a bit of a catch-22. Either I don’t export the interface and get warnings in Qsys (and no assurance that the correct connections are made during fitting), or I do export the interface and get errors or incorrect pin mapping when fitting the design in Quartus.

Is there some way to confirm that the connections are made to the correct pins if I don't export them from the lower level?

What can I do to either get rid of the warnings (and make sure the pin connections are made) in the first case, or get rid of the errors and extraneous connections in the second?

Thanks,

-phil

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't remember the exact names, but if you go in the device options (IIRC it's a button in the window that lets you choose the FPGA) there is a tab about the I/O options, and you need to set all of the pins used with EPCS as regular I/O. If you don't do that then Quartus marks these pins as reserved and you can't use them in the pin planner.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    If you don't do that then Quartus marks these pins as reserved and you can't use them in the pin planner.

    --- Quote End ---

    Daixiwen,

    Thank you. Is that necassary even if I want to use the pins as EPCS pins? I don't want to use them as general purpose I/O, they will be connected to a serial Flash for FPGA configuration. It seems to me that Quartus should automatically make the connection from the EPCS controller to the reserved EPCS pins and I shouldn't configure them as I/O's.

    -phil
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes. IIRC with the old Cyclones those pins were hidden, but since the Cyclone III (at least) the FPGA programming pins can either be disabled after configuration, or used as regular I/O.

    So if you want to access the EPCS from your application, you need to declare those pins as regular I/O after configuration, and connect them to the EPCS controller in SOPC builder/QSys.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Yes. IIRC with the old Cyclones those pins were hidden, but since the Cyclone III (at least) the FPGA programming pins can either be disabled after configuration, or used as regular I/O.

    So if you want to access the EPCS from your application, you need to declare those pins as regular I/O after configuration, and connect them to the EPCS controller in SOPC builder/QSys.

    --- Quote End ---

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am facing the same problem, I have configured the dual purpose pins as User I/O but i am still getting...

    Error (176310): Can't place multiple pins assigned to pin location Pin_12 (IOPAD_X0_Y27_N7)

    Info (176311): Pin epcs_adso is assigned to pin location Pin_12 (IOPAD_X0_Y27_N7)

    Info (176311): Pin ~ALTERA_ASDO_DATA1~ is assigned to pin location Pin_12 (IOPAD_X0_Y27_N7)

    Error (176310): Can't place multiple pins assigned to pin location Pin_14 (IOPAD_X0_Y25_N0)

    Info (176311): Pin epcs_nce is assigned to pin location Pin_14 (IOPAD_X0_Y25_N0)

    Info (176311): Pin ~ALTERA_FLASH_nCE_nCSO~ is assigned to pin location Pin_14 (IOPAD_X0_Y25_N0)

    Error (176310): Can't place multiple pins assigned to pin location Pin_23 (IOPAD_X0_Y22_N0)

    Info (176311): Pin epcs_dclk is assigned to pin location Pin_23 (IOPAD_X0_Y22_N0)

    Info (176311): Pin ~ALTERA_DCLK~ is assigned to pin location Pin_23 (IOPAD_X0_Y22_N0)

    Error (176310): Can't place multiple pins assigned to pin location Pin_24 (IOPAD_X0_Y22_N7)

    Info (176311): Pin epcs_data0 is assigned to pin location Pin_24 (IOPAD_X0_Y22_N7)

    Info (176311): Pin ~ALTERA_DATA0~ is assigned to pin location Pin_24 (IOPAD_X0_Y22_N7)

    Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01

    Error (171000): Can't fit design in device

    Error: Quartus II 32-bit Fitter was unsuccessful. 5 errors, 3 warnings

    Error: Peak virtual memory: 345 megabytes

    Error: Processing ended: Tue Sep 11 14:56:58 2012

    Error: Elapsed time: 00:00:33

    Error: Total CPU time (on all processors): 00:00:18

    Error (293001): Quartus II Full Compilation was unsuccessful. 7 errors, 987 warnings

    Please help.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I did the following to compile it rite and the whole thing worked fine.. thanks to all who gave ur valuable help.

    1. Make all dual purpose pins as User I/Os in Device settings.

    2. Assignments > Device > Device and Pin Option > Configuration > Disable the "Enable input tri-state on active configuration pins in user mode"

    thanks once again !!