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Altera_Forum
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13 years ago

Errors or Warnings when using EPCS controller in hierarchical design

I have a hierarchical design with an EPCS controller instantiated in the bottom level. I am using a Cyclone IV with a 256 pin FPGA (EP4CE15F17). In the EPCS controller there is a Conduit Endpo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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If you don't do that then Quartus marks these pins as reserved and you can't use them in the pin planner.

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Daixiwen,

Thank you. Is that necassary even if I want to use the pins as EPCS pins? I don't want to use them as general purpose I/O, they will be connected to a serial Flash for FPGA configuration. It seems to me that Quartus should automatically make the connection from the EPCS controller to the reserved EPCS pins and I shouldn't configure them as I/O's.

-phil