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Altera_Forum
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13 years ago

Errors or Warnings when using EPCS controller in hierarchical design

I have a hierarchical design with an EPCS controller instantiated in the bottom level. I am using a Cyclone IV with a 256 pin FPGA (EP4CE15F17). In the EPCS controller there is a Conduit Endpo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I don't remember the exact names, but if you go in the device options (IIRC it's a button in the window that lets you choose the FPGA) there is a tab about the I/O options, and you need to set all of the pins used with EPCS as regular I/O. If you don't do that then Quartus marks these pins as reserved and you can't use them in the pin planner.