Forum Discussion
New Contributorerror when compiling Arria10 Hard IP for PCIe example design
My FPGA ：Arria 10 10AT115S2F45E2SG
According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration.
When i compile the example design, i met some errors:
I do not konw how to solve this problem, Please help...
By the way, when i configure the PCIe at Gen2 *8, the compiling of the example design succeed., but error with PCIe Gen3*8.
6 Replies
AnandRaj_S_IntelRegular Contributor
Hi,
Which version of Quartus is used ?
Attache complete message log?
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
巍隗First，thanks for your attention.
Quartus Version: 18.1 pro(windows 10)
Attachment is the log:
- AnandRaj_S_Intel
Hi,
we acknowledge the issue, Will come back on this.
Attached Log.
Best Regards
ARS
(This message was posted on behalf of Intel Corporation)
- JosephC_Intel
Contributor
Hi 巍隗,
Just to let you know we've submitted an internal bug for this case. Currently we are waiting for engineering to assign this case.
Will keep you posted if we hear from them.
Thanks,
Joseph
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