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巍隗's avatar
巍隗
Icon for New Contributor rankNew Contributor
7 years ago

error when compiling Arria10 Hard IP for PCIe example design

My FPGA ：Arria 10 10AT115S2F45E2SG According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration. ...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

we acknowledge the issue​, Will come back on this.

Attached Log.

Best Regards

ARS

(This message was posted on behalf of Intel Corporation)