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巍隗
New Contributor
New Contributorerror when compiling Arria10 Hard IP for PCIe example design
My FPGA ：Arria 10 10AT115S2F45E2SG According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration. ...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi,
we acknowledge the issue, Will come back on this.
Attached Log.
Best Regards
ARS
(This message was posted on behalf of Intel Corporation)
