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巍隗's avatar
巍隗
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7 years ago

error when compiling Arria10 Hard IP for PCIe example design

My FPGA ：Arria 10 10AT115S2F45E2SG According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration. ...
巍隗's avatar
巍隗
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7 years ago

First，thanks for your attention.

Quartus Version: 18.1 pro(windows 10)

Attachment is the log: