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巍隗's avatar
巍隗
Icon for New Contributor rankNew Contributor
7 years ago

error when compiling Arria10 Hard IP for PCIe example design

My FPGA ：Arria 10 10AT115S2F45E2SG According to the user guide，i have generrated a A10 PCIe example design, the following figure is details about my configuration. ...
JosephC_Intel's avatar
JosephC_Intel
Icon for Contributor rankContributor
7 years ago

Hi 巍隗,

Just to let you know we've submitted an internal bug for this case. Currently we are waiting for engineering to assign this case.

Will keep you posted if we hear from them.

Thanks,

Joseph

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  • DNguy4's avatar
    DNguy4
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    is this problem solved? are you able to do the HW test on the design example?

    • LSant1's avatar
      LSant1
      Icon for Occasional Contributor rankOccasional Contributor
      7 years ago

      This issue seems to be about regenerating IP files. Once IP core files are regenerated, compilation should work fine.