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slolson's avatar
slolson
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1 year ago
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Error: spi_0: Failed to find module spi_spi_0

I am trying to generate the SPI (4 Wire Serial) Intel FPGA IP core, but the platform designer fails to generate the HDL. It looks like it could be due to "Info: spi_0: Illegal division by zero at /tools/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330." Please advise. Thanks in advance.

Hdl
Platform
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Please don't export the clock and reset ports then connect those ports to the clock source.


    Thanks,

    regards,

    Sheng


11 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Are you trying to create just the IP to instantiate in your design or are you creating a Platform Designer system that includes this IP? If it's the former, you should be adding it to your Quartus project from the IP Catalog in Quartus itself, not in an empty Platform Designer system like you are showing here.

    If you're trying to create a system design that includes the IP, I'm not sure if you're getting the error because the rest of the system is empty, which would be odd.

    But better to understand what your use case is here first.

    • slolson's avatar
      slolson
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      1 year ago

      Thanks for your reply. My use case is actually just the former -- just looking to utilize the standalone IP. However, I have noticed multiple cores are only available in the IP catalog found through the Platform Designer, not the regular IP Catalog in Quartus. The SPI (4 Wire Serial) Intel FPGA IP core happens to be one of these. Attached is a screenshot of SPI results in the regular IP Catalog. Perhaps I am missing something?

  • sstrell's avatar
    sstrell
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    1 year ago

    What are you trying to connect to with this interface?

    • slolson's avatar
      slolson
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      1 year ago

      I am sending data from existing buffers in my design to an external MCU.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Could you double click the IP to see any error settings configuration?

    If got error, it'll not be generated.


    Thanks,

    Regards,

    Sheng


    • slolson's avatar
      slolson
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      1 year ago

      Yes, no errors after configuration before generating HDL.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Please don't export the clock and reset ports then connect those ports to the clock source.


    Thanks,

    regards,

    Sheng


    • slolson's avatar
      slolson
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      1 year ago

      That worked! Thank you. Why was the clock source needed in this case but not always using other IP cores in Platform Designer?

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    That SPI IP is always associated with other ip. So please generate it together with other IPs in .qsys system instead of standalone.


    • slolson's avatar
      slolson
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      1 year ago

      I see. To clarify, I was wondering why this IP requires a clock source, whereas others don't. What makes this one different? Thank you.